Patents by Inventor Shirish A. Shah

Shirish A. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080147295
    Abstract: A system includes a controller configured to estimate a brake specific nitrogen oxide emission of an engine based on a plurality of sensed parameters of the engine. The controller is also configured to control one or more control variables of the engine to reduce specific fuel consumption while ensuring compliance of brake specific nitrogen oxide emissions within predetermined limits.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Manthram Sivasubramaniam, Paul Kenneth Houpt, Roy James Primus, Sunil Shirish Shah
  • Publication number: 20080147365
    Abstract: A methodology and system is disclosed which addresses outstanding needs of refiners to process cheaper crudes or blends of crudes. This method and system comprises a number of steps, including characterizing the impact of various constituents in the crude which result in fouling of heat exchangers; estimating model parameters; monitoring and predicting qualitative and quantitative performance; and determining optimal dosage of chemical treatments.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Inventors: Vijaysai Prasad, Yatin Tayalia, Sunil Shirish Shah, Collin W. Cross
  • Patent number: 7341742
    Abstract: A process and pharmaceutical composition containing simethicone and magnesium carbonate allows a higher production rate of simethicone containing tablets and a more consistent end product tablet. The magnesium carbonate prevents sticking of simethicone to tablet compressing apparatuses, and may also prevent sticking of other excipients to tablet compressing apparatuses.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 11, 2008
    Assignee: L. Perrigo Company
    Inventors: Douglas W. Danielson, Steven S. Schuehle, Shirish A. Shah
  • Patent number: 7127336
    Abstract: An apparatus for controlling a railway consist, the apparatus comprising: a consist model adapted for computing an objective function from a set of candidate driving plans and a set of model parameters; a parameter identifier adapted for calculating the model parameters from a set of consist measurements; and a trajectory optimizer adapted for generating the candidate driving plans and for selecting an optimal driving plan to optimize the objective function subject to a set of terminal constraints and operating constraints.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: October 24, 2006
    Assignee: General Electric Company
    Inventors: Paul Kenneth Houpt, Harry Kirk Mathews, Jr., Sunil Shirish Shah
  • Publication number: 20060201802
    Abstract: A system and method increase yield from semiconductor wafer electroplating. The aspects include a semiconductor wafer, the semiconductor wafer comprising a plurality of die areas. A plating ring for holding the semiconductor wafer in position during electroplating is also included, the plating ring substantially surrounding a circumference of the semiconductor wafer and having a width that varies in order to avoid overlap near edge die areas of the semiconductor wafer.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 14, 2006
    Inventors: Mohan Nagar, Shirish Shah
  • Publication number: 20060128072
    Abstract: A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.
    Type: Application
    Filed: December 13, 2004
    Publication date: June 15, 2006
    Inventors: Sarathy Rajagopalan, Kishor Desai, Shirish Shah
  • Publication number: 20060099736
    Abstract: A method of underfilling an integrated circuit that is mounted to a first side of a package substrate having an opposing second side. A void is provided, which extends completely through the package substrate and is disposed under the integrated circuit. The package substrate is disposed with the second side up and the first side and the integrated circuit down. An underfill material is dispensed into the void on the second side of the package substrate. The underfill material thereby flows first through the void and then between the first side of the package substrate and the integrated circuit.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 11, 2006
    Inventors: Mohan Nagar, Mukul Joshi, Shirish Shah
  • Publication number: 20060070715
    Abstract: A method of casting a refractory article. The method includes providing a mold formed from a slurry composition comprising plaster and fibers and adding a refractory composition to the mold. The method also includes allowing the refractory composition to set. The refractory composition comprises colloidal silica.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Inventors: Charles Connors, Shirish Shah
  • Publication number: 20050061471
    Abstract: A slurry composition for a mold and method of use thereof. The slurry composition includes about 45-80% by weight alumina, about 10-30% by weight silicon carbide, and about 10-50% by weight colloidal silica. In one aspect, the alumina component comprises a material selected from the group consisting of brown fused alumina, white fused alumina, tabular alumina, calcined alumina, and mixtures thereof. In another aspect, the composition includes fumed silica at 2-5% by weight. The composition may also include a setting agent at 0.05-2% by weight.
    Type: Application
    Filed: September 24, 2003
    Publication date: March 24, 2005
    Inventors: George Connors, Shirish Shah
  • Publication number: 20040239350
    Abstract: Probe cards for measuring package interconnect impedance. A first probe card includes a package having solder balls on a first surface, and an electrically conductive material on a second surface. The electrically conductive surface is configured to electrically contact bumps on the substrate. The solder balls are mountable to a test head inter phase board of the tester. The probe card does not have any probe pins, and is configured to make electrical contact with bumps on the substrate without using probe pins. A second probe card includes a substrate with solder balls on one side and solder on pad (SOP) on the other side. Vertical probe pins contact the SOP and act as an interface between a tester and solder bumps on a wafer.
    Type: Application
    Filed: October 23, 2003
    Publication date: December 2, 2004
    Inventors: Mohan R. Nagar, Kishor Desai, Shirish Shah
  • Patent number: 6806119
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: October 19, 2004
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Patent number: 6763291
    Abstract: An apparatus for controlling a plurality of locomotives, the locomotives being responsive to a plurality of discrete actual commands, the apparatus comprising: a combination generator adapted for generating combinations of the discrete actual commands to yield a command combination set; a performance calculator adapted for calculating a performance parameter set from the command combination set; a feasible combination selector adapted for selecting a feasible combination subset from the command combination set as a function of a discrete performance setpoint, a performance tolerance, and the performance parameter set; an objective function calculator adapted for calculating an objective function set from the feasible combination subset; and an optimal command selector adapted for selecting an optimal command combination from the feasible combination subset corresponding to an optimum value of the objective function set.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: July 13, 2004
    Assignee: General Electric Company
    Inventors: Paul Kenneth Houpt, Sunil Shirish Shah, Harry Kirk Mathews, Jr., David So Keung Chan, Manthram Sivasubramaniam, Raj Mohan Bharadwaj, Purnaprajna Raghavendra Mangsuli, Venkateswaran Narayanan
  • Publication number: 20040121519
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Application
    Filed: July 30, 2003
    Publication date: June 24, 2004
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Publication number: 20040070073
    Abstract: A package substrate having pads for receiving an integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. In this manner, additional structures such as solder on the pads do not need to be added, and coined, in order to ensure a minimum gap between the package substrate and the monolithic integrated circuit. The pads may be formed of at least one of copper, nickel, and gold. Also described is a packaged integrated circuit having a package substrate with pads for receiving a monolithic integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. The monolithic integrated circuit is attached to the pads with solder bumps.
    Type: Application
    Filed: October 15, 2002
    Publication date: April 15, 2004
    Inventors: Shirish Shah, Zafer S. Kutlu, Kumar Nagarajan
  • Publication number: 20040063664
    Abstract: A process and pharmaceutical composition containing simethicone and magnesium carbonate allows a higher production rate of simethicone containing tablets and a more consistent end product tablet. The magnesium carbonate prevents sticking of simethicone to tablet compressing apparatuses, and may also prevent sticking of other excipients to tablet compressing apparatuses.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Douglas W. Danielson, Steven S. Schuehle, Shirish A. Shah
  • Patent number: 6639321
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: October 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Patent number: 6395097
    Abstract: The present invention is a method for cleaning the cavities in electronic components by providing a semiconductor component having an outside surface and a cavity therein. The component including hole in the outside surface enabling fluid flow in to or out of the cavity. The component is immersed in a solvent bath where solvent is flowed into the cavity using the hole, the solvent cleaning the cavity and then optionally being evacuated from the cavity. Specifically, the principles of the present invention may be used to clean the underfill space of a flip-chip package. The flip-chip package includes a packaging substrate with an evacuation port passing through the bulk of the packaging substrate such that the port is in communication with the underfill space and a bottom surface with the packaging substrate. This assembly is immersed in a solvent filled solvent bath. Solvent is drawn into the underfill space through said port. Alternatively, solvent may be injected into the underfill space through the port.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: May 28, 2002
    Assignee: LSI Logic Corporation
    Inventors: Abhay Maheshwari, Shirish Shah
  • Patent number: 6270807
    Abstract: A chewable dosage form containing a histamine H2-receptor antagonist in an amount which is effective to treat a gastrointestinal disorder is provided in a palatably acceptable form. The dosage form comprises granules containing the histamine H2-receptor antagonist, which are provided with a taste-masking coating comprising a water-insoluble, water-permeable methacrylate ester copolymer in which the coating is applied to the granules in an amount which provides a taste-masking effect for a relatively short period during which the composition is being chewed by a patient, but which allows substantially immediate release of the histamine H2-receptor antagonist after the composition has been chewed and ingested.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: August 7, 2001
    Assignee: L. Perrigo Company
    Inventors: Douglas Willard Danielson, Shirish A. Shah
  • Patent number: 6126969
    Abstract: An orally administrable sustained-release dosage form includes particles of an active pharmaceutical ingredient which is coated with a polymeric material that is water-insoluble, but water-permeable and water-swellable, so that the sustained-release dosage form provides controlled release which is independent of certain variable physiological factors such as pH. In accordance with one aspect of the invention, the active pharmaceutical ingredient is acetaminophen and the coated acetaminophen particles are combined with uncoated acetaminophen particles to provide a combination immediate-release/sustained-release dosage form.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: October 3, 2000
    Assignee: L. Perrigo Company
    Inventors: Shirish A. Shah, Chris Y. Ho
  • Patent number: 6113945
    Abstract: The medicament of the present invention and its process of manufacturing employs a caplet or tablet core with a clear or single color uniform covering which can be applied either through an enrobing process, by spraying or by a single dip-coating step. The core itself can have a first color or be colorless, and its clear or single color covering has the outer surface of one end or one side colored by a suitable dye to provide a two-color appearance. The dye can be applied by dipping or spray painting with a suitable jet-spraying apparatus. In a preferred embodiment, the covering is of a clear gelatinous material.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: September 5, 2000
    Assignee: L. Perrigo Company
    Inventors: Richard L. Jacobs, Shirish A. Shah