Patents by Inventor Shishir Ray

Shishir Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180040505
    Abstract: A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide layer is formed in the trench. A diffusionless anneal process is performed to densify the first oxide layer. The first oxide layer is recessed to define a recess. A second oxide layer is formed in the recess.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Sandeep Gaan, Shishir Ray, Vikrant Chauhan
  • Patent number: 9673039
    Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Yiqun Liu, Jin Ping Liu, Fabio D'Addamio, Sandeep Gaan
  • Patent number: 9640423
    Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 2, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Bharat Krishnan, Shishir Ray, Jinping Liu
  • Patent number: 9570291
    Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
  • Publication number: 20170033178
    Abstract: Integrated circuits and methods for producing the same are provided. In accordance with one embodiment a method of producing an integrated circuit includes forming a trench defined by a first material. The trench is filled with a second material to produce a gap defined within the second material, where the second material is in a solid state. The second material is reflowed within the trench to reduce a volume of the gap, and the second material is then solidified within the trench.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Inventors: Bharat Krishnan, Shishir Ray, Jinping Liu
  • Patent number: 9559166
    Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Bharat Krishnan, Min-hwa Chi
  • Publication number: 20170018426
    Abstract: Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
  • Publication number: 20160284540
    Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 ? thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 29, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shishir RAY, Yiqun LIU, Jin Ping LIU, Fabio D'ADDAMIO, Sandeep GAAN
  • Patent number: 9412658
    Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 9, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Oleg Gluschenkov, Siddarth A. Krishnan, Joyeeta Nag, Andrew H. Simon, Shishir Ray
  • Publication number: 20160225852
    Abstract: Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shishir RAY, Bharat KRISHNAN, Min-hwa CHI
  • Publication number: 20160086849
    Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventors: Oleg Gluschenkov, Siddarth A. Krishnan, Joyeeta Nag, Andrew H. Simon, Shishir Ray
  • Publication number: 20150287824
    Abstract: Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Shishir Ray, Jin Ping Liu, Bharat Krishnan
  • Patent number: 9076645
    Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Sandeep Gaan, Jin Ping Liu, Zhiguo Sun