Patents by Inventor Shiu-Ko Jangjian

Shiu-Ko Jangjian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797094
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate. The image sensor device further includes a filter partially surrounded by the dielectric layer. The filter has a protruding portion protruding from a bottom surface of the dielectric layer. In addition, the image sensor device includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the protruding portion of the filter.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Volume Chien, Yun-Wei Cheng, Shiu-Ko Jangjian, Zhe-Ju Liu, Kuo-Cheng Lee, Chi-Cherng Jeng
  • Patent number: 10797176
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Publication number: 20200295193
    Abstract: A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Cheng-Ta WU, Chii-Ming WU, Shiu-Ko JANGJIAN, Kun-Tzu LIN, Lan-Fang CHANG
  • Publication number: 20200266069
    Abstract: A device includes a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile. The device further includes a contact plug electrically connected to the protrusion.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: Chia-Yang WU, Shiu-Ko JANGJIAN, Keng-Chuan CHANG, Ting-Siang SU
  • Publication number: 20200266110
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Inventors: Shiu-Ko JANGJIAN, Tzu Kai LIN, Chi-Cherng JENG
  • Patent number: 10749278
    Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive: the suppressor additive: the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-Nan Nian, Jyun-Ru Wu, Shiu-Ko Jangjian, Yu-Ren Peng, Chi-Cheng Hung, Yu-Sheng Wang
  • Publication number: 20200251577
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang WU, Shiu-Ko JANGJIAN, Ting-Chun WANG, Yung-Si YU
  • Publication number: 20200251383
    Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
    Type: Application
    Filed: April 17, 2020
    Publication date: August 6, 2020
    Inventors: Chung-Wen WU, Shiu-Ko JANGJIAN, Chien-Wen CHIU, Chien-Chung CHEN
  • Patent number: 10727137
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Tzu Kai Lin, Chi-Cherng Jeng
  • Patent number: 10720386
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20200173051
    Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.
    Type: Application
    Filed: November 7, 2019
    Publication date: June 4, 2020
    Inventors: Jun-Nan Nian, Shiu-Ko JANGJIAN, Ting-Chun WANG, Ing-Ju LEE, Yu-Ren PENG, Yao-Hsiang LIANG
  • Publication number: 20200176310
    Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 4, 2020
    Inventors: Jun-Nan Nian, Shiu-Ko JANGJIAN, Yu-Ren PENG, Yao-Hsiang LIANG, Ting-Chun WANG
  • Patent number: 10672909
    Abstract: A semiconductor device including a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material, a second portion doped with a large species material, and a third portion being undoped by the oxygen-containing material and the large species material.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Shiu-Ko Jangjian, Kun-Tzu Lin, Lan-Fang Chang
  • Patent number: 10658252
    Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ming Lin, Wei-Ken Lin, Shiu-Ko JangJian, Chun-Che Lin
  • Patent number: 10658186
    Abstract: A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Keng-Chuan Chang, Ting-Siang Su
  • Publication number: 20200152795
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Cheng-Ta WU, Cheng-Wei CHEN, Shiu-Ko JANGJIAN, Ting-Chun WANG
  • Publication number: 20200152684
    Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventors: Volume Chien, Yun-Wei Cheng, I-I Cheng, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 10629708
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Ting-Chun Wang, Yung-Si Yu
  • Publication number: 20200118869
    Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chung-Wen WU, Shiu-Ko JANGJIAN, Chien-Wen CHIU, Chien-Chung CHEN
  • Publication number: 20200098883
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin