Patents by Inventor Shivani Gupta

Shivani Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6864920
    Abstract: A circuit and method for increasing the dynamic range of CMOS image sensors designed with a thin gate oxide layer. The circuit includes a high voltage supply circuit and a high voltage level shifter circuit. The high voltage supply circuit is configured to supply a voltage to the shifter circuit. The voltage has a voltage level higher than the maximum supply voltage of the associated fabrication process. The shifter circuit is configured to output a high reset signal based on a reset signal generated to reset a pixel circuit of a pixel array. Instead of the reset signal, the high reset signal is coupled to a gate of the reset transistor in the pixel circuit. The high reset signal allows the reset transistor to maintain a gate to source potential less than the maximum supply voltage even when the high reset signal is greater than the maximum supply voltage.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: March 8, 2005
    Assignee: Eastman Kodak Company
    Inventors: Willem J. Kindt, Christina P. Phan, Shivani Gupta
  • Patent number: 6828851
    Abstract: A charge-pump circuit generates a constant voltage higher than the available power supply. A feedback path maintains the voltage at a constant level in spite of power supply, temperature and process variations. This charge pump circuit includes a switched capacitor interface arranged to generate a target voltage that is used to activate and deactivate a bypass capacitor interface to maintain the constant voltage. The bypass capacitor interface is configured to complete the feedback path. The feedback helps to ensure that node n1, that is coupled to the output of the charge pump, stays at a constant potential, irrespective of the power supply voltage.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: December 7, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Bumha Lee, Shivani Gupta, Christina Phan
  • Patent number: 6438562
    Abstract: A method, system and product for coordinating a parallel update for a global index of an indexed table involves a coordinator process and slave processes. The coordinator process receives index maintenance records from data manipulation slaves for an indexed table. Each index maintenance record includes a value for an index key of a global index of the table. The coordinator process computes index key value ranges and sends each range to an index update slave. Each slave updates the global index using just the index maintenance records with key values in its respective range, thus avoiding contention among the slaves and increasing clustering so that scaleable parallelism may be more closely attained. Techniques are also described for deferring the maintenance of global indexes relative to the time when the table on which they are built is changed.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: August 20, 2002
    Assignee: Oracle Corporation
    Inventors: Shivani Gupta, William H. Waddington, Benoit Dageville
  • Patent number: 6430550
    Abstract: Techniques are provided for executing distinct aggregation operations in a manner that is more scalable and efficient than prior techniques. A three-stage technique is provided to parallelize aggregation operations that involve both grouping and multiple distinct-key columns. Such queries are handled by splitting rows into as many pieces as there are distinct aggregates in the query, and processing the row pieces. During the first-stage, a set of slave processes scans the rows of the base tables and performs partial duplicate elimination. During the second-stage, a set of slave processes completes the duplicate elimination and performs partial set function aggregation. During the third-stage, a third set of slave processes completes the set aggregation to produce the results of the distinct aggregation operation.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: August 6, 2002
    Assignee: Oracle Corporation
    Inventors: John Leo, Cetin Ozbutun, William H. Waddington, Shivani Gupta
  • Patent number: 6380791
    Abstract: An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e.g.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: April 30, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Shivani Gupta, Christina Phan