Patents by Inventor Shivasubramanian Balasubramanian

Shivasubramanian Balasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923443
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
  • Publication number: 20200350396
    Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Shivasubramanian Balasubramanian, Dilan Seneviratne
  • Publication number: 20200312793
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Brandon C. Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D. Ecton
  • Patent number: 10756161
    Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Shivasubramanian Balasubramanian, Dilan Seneviratne
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM
  • Publication number: 20200006463
    Abstract: A semiconductor package substrate includes an integral magnetic-helical inductor that is assembled during assembly of the semiconductor package substrate. The integral magnetic-helical inductor is located within a die footprint within the semiconductor package substrate.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Shivasubramanian Balasubramanian, Dilan Seneviratne
  • Publication number: 20190252102
    Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.
    Type: Application
    Filed: February 12, 2018
    Publication date: August 15, 2019
    Applicant: INTEL CORPORATION
    Inventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian