Patents by Inventor Shizuki NAKAJIMA

Shizuki NAKAJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11417625
    Abstract: A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 16, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shizuki Nakajima
  • Publication number: 20200411465
    Abstract: A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventor: Shizuki Nakajima
  • Patent number: 10804238
    Abstract: A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: October 13, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shizuki Nakajima
  • Patent number: 10476454
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20190181816
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Patent number: 10256778
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20180302045
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Publication number: 20180240771
    Abstract: A method for manufacturing a semiconductor device includes (i) a step of preparing a first semiconductor chip having a first electrode pad thereon and a second semiconductor chip having a second electrode pad thereon and larger in thickness than the first semiconductor chip, the second electrode pad being larger in size than the first electrode pad, (ii) a step of mounting the first semiconductor chip and the second semiconductor chip on the same planarized surface of a substrate having a uniform thickness, (iii) a step of bonding a ball formed by heating and melting a bonding wire to the second electrode pad, (iv) a step of first-bonding the bonding wire to the first electrode pad, and (v) a step of second-bonding the bonding wire to the ball.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Inventor: Shizuki Nakajima
  • Patent number: 10044330
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 7, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Ishihara, Seiko Ono, Yusuke Shimamune, Fuminori Morisawa, Shizuki Nakajima, Yuri Honda, Kazuhiro Koshio, Masato Sato
  • Publication number: 20180083581
    Abstract: A power amplifier module includes a first current source that outputs a first current corresponding to a level control voltage for controlling a signal level of an amplified signal, a second current source that outputs a second current corresponding to the level control voltage, a first transistor in which an input signal and a first bias current are supplied to a base and an emitter is grounded, a second transistor in which an emitter is connected to a collector of the first transistor, the second current is supplied to a base, and a first amplified signal obtained by amplifying the input signal is output from a collector, and a third transistor in which the first current is supplied to a collector, a bias control current or voltage is supplied to a base, and the first bias current is supplied from an emitter to the base of the first transistor.
    Type: Application
    Filed: September 20, 2017
    Publication date: March 22, 2018
    Inventors: Shota ISHIHARA, Seiko ONO, Yusuke SHIMAMUNE, Fuminori MORISAWA, Shizuki NAKAJIMA, Yuri HONDA, Kazuhiro KOSHIO, Masato SATO
  • Patent number: 8742499
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
  • Publication number: 20100109052
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 6, 2010
    Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE