Patents by Inventor Shlomo Raikin

Shlomo Raikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10324513
    Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 18, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch, Lavi Koch
  • Patent number: 10223204
    Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
  • Publication number: 20190065160
    Abstract: A method and apparatus for hybrid pre and post-retire tentative access tracking is herein described. Access tracking is often performed during execution of critical sections, which may be defined by traditional locks or transactional memory instructions. Pre-retire accesses to memory are performed to update tracking information for access during execution of a critical section. However, post-retire updates to tracking information are performed for subsequent consecutive critical section accesses in a pipeline when a previous end critical section operation is retired.
    Type: Application
    Filed: November 7, 2007
    Publication date: February 28, 2019
    Inventors: Haitham Akkary, Shlomo Raikin, Ravi Rajwar, Gad Sheaffer, Srikanth T. Srinivasan
  • Patent number: 10164905
    Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 25, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ofer Hayut, Noam Bloch, Shlomo Raikin, Liran Liss
  • Patent number: 10152441
    Abstract: Peripheral apparatus for use with a host computer includes an add-on device, which includes a first network port coupled to one end of a packet communication link and add-on logic, which is configured to receive and transmit packets containing data over the packet communication link and to perform computational operations on the data. A network interface controller (NIC) includes a host bus interface, configured for connection to the host bus of the host computer and a second network port, coupled to the other end of the packet communication link. Packet processing logic in the NIC is coupled between the host bus interface and the second network port, and is configured to translate between the packets transmitted and received over the packet communication link and transactions executed on the host bus so as to provide access between the add-on device and the resources of the host computer.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: December 11, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Liran Liss, Shachar Raindel, Shlomo Raikin, Adi Menachem, Yuval Itkin
  • Patent number: 10152451
    Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Shlomo Raikin, Stanislav Shwartsman, Gal Ofir, Igor Yanover, Guy Patkin, Ofer Levy
  • Publication number: 20180349292
    Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 6, 2018
    Inventors: Gilad Tal, Gil Moran, Miriam Menes, Gil Kopilov, Shlomo Raikin
  • Patent number: 10146737
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir
  • Patent number: 10135739
    Abstract: A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 20, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shachar Raindel, Shlomo Raikin, Liran Liss
  • Patent number: 10120832
    Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 6, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shachar Raindel, Idan Burstein, Noam Bloch, Shlomo Raikin
  • Patent number: 10082858
    Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: September 25, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch
  • Patent number: 10031857
    Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 24, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Shlomo Raikin, Idan Burstein, Michael Kagan
  • Patent number: 9990287
    Abstract: An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Raanan Sade, Robert Valentine, Julius Yuli Mandelblat, Ron Shalev, Larisa Novakovsky
  • Patent number: 9971705
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Patent number: 9925492
    Abstract: Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: March 27, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Shlomo Raikin, Liran Liss, Ariel Shachar, Noam Bloch, Michael Kagan
  • Publication number: 20180060049
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
  • Publication number: 20170351641
    Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
    Type: Application
    Filed: April 18, 2017
    Publication date: December 7, 2017
    Inventors: ZEEV SPERBER, ROBERT VALENTINE, SHLOMO RAIKIN, STANISLAV SHWARTSMAN, GAL OFIR, IGOR YANOVER, GUY PATKIN, OFER LEVY
  • Patent number: 9785462
    Abstract: A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin
  • Publication number: 20170255559
    Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.
    Type: Application
    Filed: March 2, 2016
    Publication date: September 7, 2017
    Inventors: Idan Burstein, Diego Crupnicoff, Shlomo Raikin, Michael Kagan
  • Patent number: 9753889
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir