Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: A computational apparatus for implementing a neural network model having multiple neurons that evaluate an activation function, the apparatus including a memory and circuitry. The memory is configured to hold values of a difference-function, each value being a respective difference between the activation function and a predefined baseline function. The circuitry is configured to evaluate the neural network model, including, for at least one of the neurons: evaluate the baseline function at the argument, retrieve from the memory one or more values of the difference-function responsively to the argument, and evaluate the activation function at the argument based on the baseline function at the argument and on the one or more values of the difference-function.

Abstract: A processor includes an internal memory and processing circuitry. The internal memory is configured to store a definition of a multi-dimensional array stored in an external memory, and indices that specify elements of the multi-dimensional array in terms of multi-dimensional coordinates of the elements within the array. The processing circuitry is configured to execute instructions in accordance with an Instruction Set Architecture (ISA) defined for the processor. At least some of the instructions in the ISA access the multi-dimensional array by operating on the multi-dimensional coordinates specified in the indices.

Abstract: Systems, and method and computer readable media that store instructions for remote direct memory access (RDMA) congestion control.

Abstract: A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.

Abstract: Systems, and method and computer readable media that store instructions for remote direct memory access (RDMA) congestion control.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: A vector processor includes a coefficient memory and a processor. The processor has an Instruction Set Architecture (ISA), which includes an instruction that approximates a mathematical function by a polynomial. The processor is configured to approximate the mathematical function over an argument, by reading one or more coefficients of the polynomial from the coefficient memory and evaluating the polynomial at the argument using the coefficients.

Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.

Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract: Data processing apparatus includes a host processor and a network interface controller (NIC), which is configured to couple the host processor to a packet data network. A memory holds a flow state table containing context information with respect to computational operations to be performed on multiple packet flows conveyed between the host processor and the network. Acceleration logic is coupled to perform the computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: An apparatus includes an input interface and compression circuitry. The input interface is configured to receive input source data. The compression circuitry in configured to set a symbol anchor value, having a highest occurrence probability among the symbol values in the input source data, to generate a bit-map by (i) for every symbol in the input source data whose symbol value is the anchor value, setting a respective bit in the bit-map to a first binary value, and (ii) for every symbol in the source data whose symbol value differs from the anchor value, setting the respective bit in the bit-map to a second binary value, and to generate compressed data including (i) the bit-map and (ii) the symbols whose symbol values differ from the symbol anchor value.

Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract: A method and apparatus for hybrid pre and post-retire tentative access tracking is herein described. Access tracking is often performed during execution of critical sections, which may be defined by traditional locks or transactional memory instructions. Pre-retire accesses to memory are performed to update tracking information for access during execution of a critical section. However, post-retire updates to tracking information are performed for subsequent consecutive critical section accesses in a pipeline when a previous end critical section operation is retired.

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.