Patents by Inventor Shlomo Raikin

Shlomo Raikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160103785
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 14, 2016
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir
  • Publication number: 20160077946
    Abstract: A method for data transfer includes receiving in a data transfer operation data to be written by a peripheral device to a specified virtual address in a random access memory (RAM) of a host computer. Upon receiving the data, it is detected that a page that contains the specified virtual address is marked as not present in a page table of the host computer. The peripheral device receives a notification that the page is not present and an estimate of a length of time that will be required to make the page available and selects a mode for handling of the data transfer operation depending upon the estimate.
    Type: Application
    Filed: September 7, 2015
    Publication date: March 17, 2016
    Inventors: Shlomo Raikin, Shachar Raindel, Noam Bloch, Liran Liss
  • Publication number: 20160077976
    Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 17, 2016
    Inventors: Shlomo Raikin, Idan Burstein, Adi Menachem, Michael Kagan
  • Patent number: 9286235
    Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
  • Publication number: 20160062442
    Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch, Lavi Koch
  • Patent number: 9268697
    Abstract: A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Ilan Pardo, Niranjan Cooray, Stanislav Shwartsman, Shlomo Raikin
  • Publication number: 20160043965
    Abstract: Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded.
    Type: Application
    Filed: June 29, 2015
    Publication date: February 11, 2016
    Inventors: Dror Goldenberg, Liran Liss, Shlomo Raikin
  • Publication number: 20150370309
    Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 24, 2015
    Inventors: Idan Burstein, Shlomo Raikin, Noam Bloch
  • Publication number: 20150347349
    Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 3, 2015
    Inventors: Shachar Raindel, Idan Burstein, Noam Bloch, Shlomo Raikin
  • Patent number: 9183161
    Abstract: An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 10, 2015
    Assignee: INTEL CORPORATION
    Inventors: Gur Hildesheim, Ittai Anati, Hisham Shafi, Shlomo Raikin, Gideon Gerzon, Uday R Savagaonkar, Carlos V Rozas, Francis X McKeen, Michael A Goldsmith, Dewan Prashant
  • Publication number: 20150293881
    Abstract: A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data.
    Type: Application
    Filed: March 11, 2015
    Publication date: October 15, 2015
    Inventors: Shlomo Raikin, Shachar Raindel, Michael Kagan
  • Publication number: 20150269116
    Abstract: Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 24, 2015
    Inventors: Shlomo Raikin, Liran Liss, Ariel Shachar, Noam Bloch, Michael Kagan
  • Publication number: 20150271244
    Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 24, 2015
    Inventors: Noam Bloch, Ariel Shachar, Michael Kagan, Lior Narkis, Shlomo Raikin
  • Publication number: 20150261720
    Abstract: A method for data storage includes configuring a driver program on a host computer to receive commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer. When the driver program receives, from an application program running on the host computer a storage access command in accordance with the protocol, specifying a storage transaction, a remote direct memory access (RDMA) operation is performed by a network interface controller (NIC) connected to the host computer so as to execute the storage transaction via a network on a remote storage device.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Noam Bloch, Shlomo Raikin, Yaron Haviv, Idan Burstein
  • Publication number: 20150261434
    Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Noam Bloch, Shlomo Raikin, Yaron Haviv, Idan Burstein
  • Publication number: 20150222547
    Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 6, 2015
    Inventors: Ofer Hayut, Noam Bloch, Shlomo Raikin, Liran Liss
  • Publication number: 20150212817
    Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.
    Type: Application
    Filed: January 29, 2015
    Publication date: July 30, 2015
    Inventors: Shlomo Raikin, Noam Bloch, Richard Graham, Ofer Hayut, Michael Kagan, Liran Liss
  • Patent number: 9027009
    Abstract: The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Lihu Rappoport, Joseph Nuzman
  • Publication number: 20150074373
    Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
    Type: Application
    Filed: June 2, 2012
    Publication date: March 12, 2015
    Inventors: Zeev Sperber, Robert Valentine, Shlomo Raikin, Stanislav Shwartsman, Gal Ofir, Igor Yanover, Guy Patkin, Levy Ofer
  • Patent number: 8972697
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Grant
    Filed: June 2, 2012
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir