Patents by Inventor Sho Ikeda

Sho Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250030342
    Abstract: Disclosed is a band gap power supply circuit including a band gap core circuit to perform control in such a way that the sum of a current flowing through a diode and a current flowing through a first current path becomes equal to the sum of a current flowing through a diode and a current flowing through a second current path, and the sum of the forward direction voltage of the diode and a voltage drop across a resistor becomes equal to the forward direction voltage of the diode; and a switch control circuit to control a switch and a switch from off to on at a time of a startup of a power supply.
    Type: Application
    Filed: October 4, 2024
    Publication date: January 23, 2025
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shimpei YAMASHITA, Sho IKEDA
  • Patent number: 12198271
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 14, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada
  • Publication number: 20240372508
    Abstract: Disclosed is a harmonic mixer including N transistors, an RF terminal, N LO terminals, an IF terminal, a series resonant circuit, and an IF matching circuit, in which when the RF frequency of a high frequency signal is identical or close to the maximum oscillation frequency of the transistors, the impedance seen from the IF terminal toward an output terminal at the RF frequency becomes low, and the impedance seen from the IF terminal toward the output terminal at an IF frequency is the combination of the impedance of the series resonant circuit and the impedance of the IF matching circuit.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shinya YOKOMIZO, Sho IKEDA, Yoshiaki MORINO
  • Publication number: 20240341495
    Abstract: A cushion body extends in a first direction, in a second direction and in third direction that is orthogonal to the first direction and the second direction. Protrusions are arranged in the first direction and in the second direction. A first slit extends in the first direction adjacent to a protrusion group, and additionally extends into the cushion body in the third direction. A second slit extends in the second direction adjacent to the protrusion group, and additionally extends into the cushion body in the third direction.
    Type: Application
    Filed: July 29, 2022
    Publication date: October 17, 2024
    Inventors: Yasuyuki NISHIKAWA, Jun YASUKAWA, Yoji SHIMURA, Hideaki MOGI, Sho IKEDA, Akihiko KAWASAKA, Hiroyuki NAGAYAMA, Kanna MATSUYAMA, Masataka OGASAWARA
  • Publication number: 20240235529
    Abstract: A filter circuit includes: a filter unit which is connected to a signal line and which has transistors and capacitors which constitute paths for N phases, and in which the transistors to which clock signals of N phases are applied electrically connect the capacitors to the signal line; and a dummy unit which has transistors and impedance parts which constitute dummy paths corresponding, respectively, to the paths for the N phases, and in which the transistors to which inverted signals of N phases are applied electrically connect the impedance parts to the signal line.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takaya MARUYAMA, Sho IKEDA, Koji TSUTSUMI
  • Patent number: 11985792
    Abstract: An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventors: Sho Ikeda, Osamu Kamimura, Kenichi Miyamoto, Akihiro Adachi
  • Publication number: 20240104844
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada
  • Patent number: 11929723
    Abstract: A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase sh
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: March 12, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Yamamoto, Koji Tsutsumi, Sho Ikeda, Masaomi Tsuru
  • Patent number: 11870447
    Abstract: A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 9, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Sho Ikeda, Akihito Hirai, Koji Tsutsumi, Masaomi Tsuru
  • Publication number: 20230332674
    Abstract: A booster lever unit includes a first lever pivotably supported by an object via a first pivotal shaft, a second lever pivotably supported by the object via a second pivotal shaft, and a linkage member that links the first lever to the second lever. The pivotal plane of the first lever is parallel to the pivotal plane of the second lever. The first lever has one end provided with an operation section, and another end provided with the first pivotal shaft, and the first lever further includes a first linker, the first linker being provided between the operation section and the first pivotal shaft and linked to the linkage member. The second lever has one end provided with an action section, and another end provided with a second linker linked to the linkage member, and the second pivotal shaft is provided between the action section and the second linker.
    Type: Application
    Filed: August 31, 2022
    Publication date: October 19, 2023
    Inventors: Sho IKEDA, Akihiro ADACHI, Osamu KAMIMURA, Kenichi MIYAMOTO, Yosuke ISHIDA
  • Patent number: 11757454
    Abstract: A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: September 12, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Sho Ikeda, Koji Tsutsumi, Masaomi Tsuru
  • Patent number: 11722289
    Abstract: In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: August 8, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Mizutani, Sho Ikeda, Kae Morita
  • Publication number: 20230171913
    Abstract: An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 1, 2023
    Applicant: Hitachi, Ltd.
    Inventors: Sho IKEDA, Osamu KAMIMURA, Kenichi MIYAMOTO, Akihiro ADACHI
  • Publication number: 20230017177
    Abstract: A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Sho IKEDA, Koji TSUTSUMI, Masaomi TSURU
  • Publication number: 20220349992
    Abstract: In a radar device, a reception antenna directly receives a chirp signal transmitted by a transmission antenna of a module other than a module to which the reception antenna belongs among a plurality of modules, a mixer generates a baseband signal by mixing a chirp signal generated by a chirp signal source and a chirp signal received by the reception antenna, and an analog-to-digital converter generates a digital signal by digital-converting the baseband signal generated by the mixer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koji TSUTSUMI, Sho IKEDA
  • Patent number: D1026503
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: May 14, 2024
    Assignee: NISHIKAWA Co., Ltd.
    Inventors: Yasuyuki Nishikawa, Jun Yasukawa, Yoji Shimura, Hideaki Mogi, Sho Ikeda, Mari Aoki
  • Patent number: D1033985
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: July 9, 2024
    Assignees: NISHIKAWA Co., Ltd., ARCHEM INC.
    Inventors: Yasuyuki Nishikawa, Jun Yasukawa, Yoji Shimura, Hideaki Mogi, Sho Ikeda, Akihiko Kawasaka, Hiroyuki Nagayama, Kanna Matsuyama, Masataka Ogasawara
  • Patent number: D1035329
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: July 16, 2024
    Assignees: NISHIKAWA Co., Ltd., ARCHEM INC.
    Inventors: Yasuyuki Nishikawa, Jun Yasukawa, Yoji Shimura, Hideaki Mogi, Sho Ikeda, Akihiko Kawasaka, Hiroyuki Nagayama, Kanna Matsuyama, Masataka Ogasawara
  • Patent number: D1036155
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 23, 2024
    Assignee: NISHIKAWA Co., Ltd.
    Inventors: Yasuyuki Nishikawa, Jun Yasukawa, Yoji Shimura, Hideaki Mogi, Sho Ikeda, Mari Aoki
  • Patent number: D1039295
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: August 20, 2024
    Assignee: NISHIKAWA Co., Ltd.
    Inventors: Yasuyuki Nishikawa, Jun Yasukawa, Yoji Shimura, Hideaki Mogi, Sho Ikeda, Mari Aoki