Patents by Inventor Sho-Shen Lee
Sho-Shen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763264Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.Type: GrantFiled: September 16, 2019Date of Patent: September 1, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
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Patent number: 10707213Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.Type: GrantFiled: November 1, 2018Date of Patent: July 7, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
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Patent number: 10707092Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.Type: GrantFiled: January 10, 2019Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
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Publication number: 20200203176Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.Type: ApplicationFiled: January 10, 2019Publication date: June 25, 2020Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Jhao-Hao Lee, Sho-Shen Lee, Chih-Yu Chiang
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Patent number: 10692785Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.Type: GrantFiled: August 8, 2018Date of Patent: June 23, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee
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Publication number: 20200111791Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.Type: ApplicationFiled: November 1, 2018Publication date: April 9, 2020Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
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Publication number: 20200013724Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.Type: ApplicationFiled: July 31, 2018Publication date: January 9, 2020Inventors: Zheng-Feng Chen, Sho-Shen Lee, En-Chiuan Liou, Hsiao-Lin Hsu, Yi-Ting Chen, Lu-Wei Kuo
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Publication number: 20200013783Abstract: The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
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Patent number: 10529667Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.Type: GrantFiled: July 31, 2018Date of Patent: January 7, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Zheng-Feng Chen, Sho-Shen Lee, En-Chiuan Liou, Hsiao-Lin Hsu, Yi-Ting Chen, Lu-Wei Kuo
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Patent number: 10453849Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.Type: GrantFiled: March 26, 2018Date of Patent: October 22, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
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Publication number: 20190273083Abstract: The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.Type: ApplicationFiled: March 26, 2018Publication date: September 5, 2019Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang, Sho-Shen Lee
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Patent number: 10373915Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.Type: GrantFiled: November 28, 2018Date of Patent: August 6, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsiao-Lin Hsu, En-Chiuan Liou, Yi-Ting Chen, Sho-Shen Lee
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Patent number: 10276395Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.Type: GrantFiled: March 21, 2018Date of Patent: April 30, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee
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Patent number: 10177094Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.Type: GrantFiled: April 16, 2018Date of Patent: January 8, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Hsiao-Lin Hsu, En-Chiuan Liou, Yi-Ting Chen, Sho-Shen Lee
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Publication number: 20180374765Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.Type: ApplicationFiled: August 8, 2018Publication date: December 27, 2018Inventors: Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee
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Publication number: 20180286692Abstract: The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.Type: ApplicationFiled: March 21, 2018Publication date: October 4, 2018Inventors: Chien-Hao Chen, Feng-Lun Wu, Chung-Ping Hsia, Sho-Shen Lee
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Patent number: 10079185Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.Type: GrantFiled: June 23, 2017Date of Patent: September 18, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chien-Hao Chen, Chien-Wei Huang, Chia-Hung Wang, Sho-Shen Lee
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Patent number: 9490217Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.Type: GrantFiled: April 15, 2015Date of Patent: November 8, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ching Lin, En-Chiuan Liou, Chia-Hung Wang, Sho-Shen Lee
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Publication number: 20160307850Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.Type: ApplicationFiled: April 15, 2015Publication date: October 20, 2016Inventors: Chia-Ching Lin, En-Chiuan Liou, Chia-Hung Wang, Sho-Shen Lee
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Patent number: 9304389Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.Type: GrantFiled: October 31, 2013Date of Patent: April 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang