Patents by Inventor Shogo Mochizuki

Shogo Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180331216
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10128372
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Patent number: 10115824
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion of the substrate, and forming a semiconductor material layer on the source/drain region. A first liner layer is deposited on the semiconductor material layer, and a second liner layer is deposited on the first liner layer. A conductive contact material is deposited on the second liner layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Ruilong Xie
  • Publication number: 20180308993
    Abstract: MIS capacitors are formed using a finned semiconductor structure. A highly doped region including the fins is formed within the structure and forms one plate of a MIS capacitor. A metal layer forms a second capacitor plate that is separated from the first plate by a high-k capacitor dielectric layer formed directly on the highly doped fins. Contacts are electrically connected to the capacitor plates. A highly doped implantation layer having a conductivity type opposite to that of the highly doped region provides electrical isolation within the structure.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Inventors: Keith E. Fogel, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180308768
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: June 16, 2018
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Publication number: 20180308766
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Publication number: 20180308767
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Application
    Filed: June 16, 2018
    Publication date: October 25, 2018
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Patent number: 10103065
    Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Alexander Reznicek, Joshua M. Rubin, Junli Wang
  • Publication number: 20180294354
    Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.
    Type: Application
    Filed: June 13, 2018
    Publication date: October 11, 2018
    Inventors: HEMANTH JAGANNATHAN, SHOGO MOCHIZUKI
  • Patent number: 10096713
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • Publication number: 20180277483
    Abstract: A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 27, 2018
    Inventors: Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi
  • Publication number: 20180277445
    Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
    Type: Application
    Filed: March 22, 2017
    Publication date: September 27, 2018
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180277446
    Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
    Type: Application
    Filed: November 13, 2017
    Publication date: September 27, 2018
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10084082
    Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Patent number: 10084065
    Abstract: During a fabrication of a semiconductor device, a recess is created in a substrate material disposed along a direction of a plane of fabrication. A layer of a removable material is formed in the recess. A bottom layer is formed above the layer of removable material. A vertical channel above the bottom layer is formed in a direction substantially orthogonal to the direction of the plane of fabrication. A gate is formed using a metal above the bottom layer and relative to the vertical channel. A tunnel is created under the bottom layer by removing the removable material from under the bottom layer such that the backside of the bottom layer forms a ceiling of the tunnel. The tunnel is filled using a conductive material such that the conductive material makes electrical contact with the backside of the bottom layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shogo Mochizuki, Junli Wang
  • Publication number: 20180269310
    Abstract: During a fabrication of a semiconductor device, a recess is created in a substrate material disposed along a direction of a plane of fabrication. A layer of a removable material is formed in the recess. A bottom layer is formed above the layer of removable material. A vertical channel above the bottom layer is formed in a direction substantially orthogonal to the direction of the plane of fabrication. A gate is formed using a metal above the bottom layer and relative to the vertical channel. A tunnel is created under the bottom layer by removing the removable material from under the bottom layer such that the backside of the bottom layer forms a ceiling of the tunnel. The tunnel is filled using a conductive material such that the conductive material makes electrical contact with the backside of the bottom layer.
    Type: Application
    Filed: May 16, 2018
    Publication date: September 20, 2018
    Applicant: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Junli Wang
  • Patent number: 10079299
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Publication number: 20180261685
    Abstract: During a fabrication of a semiconductor device, a recess is created in a substrate material disposed along a direction of a plane of fabrication. A layer of a removable material is formed in the recess. A bottom layer is formed above the layer of removable material. A vertical channel above the bottom layer is formed in a direction substantially orthogonal to the direction of the plane of fabrication. A gate is formed using a metal above the bottom layer and relative to the vertical channel. A tunnel is created under the bottom layer by removing the removable material from under the bottom layer such that the backside of the bottom layer forms a ceiling of the tunnel. The tunnel is filled using a conductive material such that the conductive material makes electrical contact with the backside of the bottom layer.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Applicant: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Junli Wang
  • Publication number: 20180254333
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Inventors: Veeraraghavan S. Basker, Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10068920
    Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed. The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alexander Reznicek, Veeraraghavan S. Basker, Shogo Mochizuki, Nicolas L. Breil, Oleg Gluschenkov