Patents by Inventor Shogo Okita

Shogo Okita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9911638
    Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion disposed inside the stage; a support portion which supports the conveyance carrier; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage, the electrostatic chuck mechanism performs an operation of applying a voltage to the electrode portion after contact of an outer circumferential portion of a holding sheet of the conveyance carrier to the stage, the operation including a voltage varying operation of increasing and decreasing an absolute value of the voltage, and the plasma generation unit generates plasma after completion of the voltage varying operation.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 6, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara
  • Publication number: 20180019099
    Abstract: A plasma processing apparatus includes: a vessel which includes a reaction chamber, atmosphere within the reaction chamber capable of being depressurized; a lower electrode which supports an object to be processed within the reaction chamber; a dielectric member which includes a first surface and a second surface opposite to the first surface, and which closes an opening of the vessel such that the first surface opposes an outside of the reaction chamber and the second surface opposes the object to be processed; and a coil which opposes the first surface of the dielectric member, and which generates plasma within the reaction chamber. The dielectric member has a groove formed in the first surface of the dielectric member, and at least a part of the coil is disposed in the groove.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Inventors: Tetsuhiro IWAI, Shogo OKITA
  • Publication number: 20180012802
    Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.
    Type: Application
    Filed: June 14, 2017
    Publication date: January 11, 2018
    Inventors: SHOGO OKITA, MITSURU HIROSHIMA, ATSUSHI HARIKAI, NORIYUKI MATSUBARA, AKIHIRO ITOU
  • Patent number: 9859144
    Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 2, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Publication number: 20170345781
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 30, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, AKIHIRO ITOU, KATSUMI TAKANO, MITSURU HIROSHIMA
  • Publication number: 20170345715
    Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 30, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, AKIHIRO ITOU, KATSUMI TAKANO, MITSURU HIROSHIMA
  • Patent number: 9799495
    Abstract: A plasma processing apparatus that performs plasma processing on a substrate held on a transport carrier including an annular frame and a holding sheet. The apparatus includes a process chamber; a process gas supply unit that supplies process gas to the process chamber; a decompressing mechanism that decompresses the process chamber; a plasma excitation device that generates plasma in the process chamber; a stage in the chamber, on which the transport carrier is loaded; a cooling mechanism for cooling the stage; a cover that partly covers the holding sheet and the frame and that has a window section through which the substrate is partly exposed to plasma; a correction member that presses the frame onto the stage and corrects warpage of the frame; and a movement device that moves the correction member. The correction member is provided separately from the cover to be covered by the cover.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 24, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shogo Okita, Bunji Miizuno, Tomohiro Okumura
  • Patent number: 9786472
    Abstract: A plasma processing apparatus performs plasma processing on a substrate held by a carrier. The carrier includes a frame disposed around the substrate and a holding sheet which holds the substrate and the frame. The plasma processing apparatus includes: a chamber; a stage which is disposed within the chamber and has an upper surface on which the carrier is mounted; a gas hole which is provided at a position of the upper surface opposing a bottom surface of the frame and through which cooling gas is supplied between the stage and the carrier; and a plasma exciting unit which generates plasma within the chamber.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 10, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tetsuhiro Iwai, Shogo Okita, Syouzou Watanabe
  • Patent number: 9780021
    Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 3, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
  • Publication number: 20170271194
    Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 21, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI, AKIHIRO ITOU
  • Publication number: 20170263526
    Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, MITSURU HIROSHIMA, SHOGO OKITA, NORIYUKI MATSUBARA, ATSUSHI HARIKAI
  • Publication number: 20170263525
    Abstract: A method of manufacturing an element chip includes an isotropic etching step of removing the first damaged region and the second damaged region through etching the first layer isotropically by exposing the substrate to first plasma after the laser scribing step. The method of manufacturing an element chip further includes a plasma, dicing step of dividing the substrate to a plurality of element chips including the element region through etching the first layer anisotropically by exposing the substrate to second plasma in a state where the second main surface is supported by a supporting member, after the isotropic etching step.
    Type: Application
    Filed: February 7, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, SHOGO OKITA, MITSURU HIROSHIMA, TUTOMU SAKURAI, NORIYUKI MATSUBARA
  • Publication number: 20170263462
    Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 14, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI
  • Publication number: 20170263500
    Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.
    Type: Application
    Filed: February 7, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, SHOGO OKITA, MITSURU HIROSHIMA, TUTOMU SAKURAI, NORIYUKI MATSUBARA
  • Publication number: 20170263502
    Abstract: The method for manufacturing an element chip includes a mounting step and a plasma dicing step. In the mounting step, a semiconductor substrate with flexibility, which has a first main surface and a second main surface located at an opposite side of the first main surface, which has a plurality element regions and a dividing region for defining the element regions, and on which a mask for covering the first main surface in the element region and for exposing the first main surface in the dividing region is formed, is mounted on a stage. In the plasma dicing step, the semiconductor substrate is diced into a plurality of element chips including the element; region by exposing the first main surface side of the semiconductor substrate to plasma on the stage and etching from the first main surface side to the second main surface while forming a groove on the dividing region.
    Type: Application
    Filed: February 9, 2017
    Publication date: September 14, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI, AKIHIRO ITOU, NORIYUKI MATSUBARA, BUNZI MIZUNO
  • Publication number: 20170263524
    Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.
    Type: Application
    Filed: February 7, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, MITSURU HIROSHIMA, SHOGO OKITA, NORIYUKI MATSUBARA, ATSUSHI HARIKAI
  • Publication number: 20170263501
    Abstract: A method for manufacturing an element chip includes a laser dicing step of dividing the substrate to a plurality of element chips including the element region by irradiating the dividing region of the substrate with laser light, in a state of supported by a supporting member and forming a damaged region on an end surface of the element chip. Furthermore, the method for manufacturing an element chip includes a protection film stacking step of stacking a protection film on the first main surface and the end surface of the element chip, after the laser dicing step and a protection film etching step of removing the protection film stacked on the first main surface through etching the protection film anisotropically by exposing the element chip to plasma, after the protection film stacking, step and remaining the protection film for covering the damaged region.
    Type: Application
    Filed: February 8, 2017
    Publication date: September 14, 2017
    Inventors: BUNZI MIZUNO, SHOGO OKITA, NORIYUKI MATSUBARA, ATSUSHI HARIKAI, MITSURU HIROSHIMA
  • Publication number: 20170256412
    Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A plasma treatment method of the substrate held by the conveyance carrier includes preparing the conveyance carrier which includes a holding sheet and a frame disposed on the outer peripheral portion of the holding sheet; bonding the substrate to the holding sheet so that the substrate is held by the conveyance carrier; and increasing tensile strength of the holding sheet. The plasma treatment method further includes placing the conveyance carrier on the stage after the bonding of the substrate and bringing the substrate into contact with the stage through the holding sheet; and performing a plasma treatment on the substrate after the placing of the conveyance carrier.
    Type: Application
    Filed: February 7, 2017
    Publication date: September 7, 2017
    Inventors: SHOGO OKITA, ATSUSHI HARIKAI
  • Publication number: 20170229365
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Application
    Filed: January 18, 2017
    Publication date: August 10, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, NORIYUKI MATSUBARA, MITSURU HIROSHIMA, MITSUHIRO OKUNE
  • Publication number: 20170229366
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Application
    Filed: January 18, 2017
    Publication date: August 10, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, NORIYUKI MATSUBARA, MITSURU HIROSHIMA, MITSUHIRO OKUNE