Patents by Inventor Shohei Asami

Shohei Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190094927
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Application
    Filed: June 18, 2018
    Publication date: March 28, 2019
    Inventors: Yuka KUWANO, Takehiko AMAKI, Toshikatsu HIDA, Shohei ASAMI
  • Publication number: 20190074283
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: August 1, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa Kojima, Toshikatsu Hida, Marie Sia, Riki Suzuki, Shohei Asami
  • Publication number: 20180091170
    Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 29, 2018
    Inventors: Shohei ASAMI, Toshikatsu HIDA
  • Patent number: 9891848
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
  • Patent number: 9875803
    Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller reads data from third memory cells included in the second memory cells by using the calculated second read voltage.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Toshikatsu Hida
  • Publication number: 20170076807
    Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller ads data from third memory cells included in the second memory cells by using the calculated second read voltage.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shohei ASAMI, Toshikatsu Hida
  • Patent number: 9568987
    Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru Anazawa, Toshikatsu Hida, Shohei Asami
  • Patent number: 9564930
    Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Toshikatsu Hida, Mitsunori Tadokoro, Yoshihisa Kojima, Shohei Asami
  • Publication number: 20160266638
    Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.
    Type: Application
    Filed: July 10, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru ANAZAWA, Toshikatsu HIDA, Shohei ASAMI
  • Patent number: 9442560
    Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shohei Asami, Toshikatsu Hida, Mitsunori Tadokoro, Hirokazu Morita
  • Publication number: 20160259576
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shohei ASAMI, Tokumasa HARA, Hiroshi YAO, Kenichiro YOSHII, Riki SUZUKI, Toshikatsu HIDA, Osamu TORII
  • Publication number: 20160072527
    Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 10, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Mitsunori TADOKORO, Yoshihisa KOJIMA, Shohei ASAMI
  • Patent number: 9251892
    Abstract: According to an embodiment, a controller specifies a first voltage range that has a first distribution quantity, a second voltage range that is adjacent to a lower voltage side of the first voltage range, and a third voltage range that is adjacent to a higher voltage side of the first voltage range. The first distribution quantity is a minimum value of the memory cells. The controller determines a read voltage by using the first voltage range, a first representative voltage value in the first voltage range, the first distribution quantity, a second distribution quantity corresponding to the second voltage range, and a third distribution quantity corresponding to the third voltage range.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shohei Asami, Toshikatsu Hida, Tokumasa Hara, Riki Suzuki
  • Patent number: 9158678
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: October 13, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Riki Suzuki, Shohei Asami, Toshikatsu Hida, Hiroshi Yao, Kazuhiro Fukutomi
  • Publication number: 20150241952
    Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.
    Type: Application
    Filed: June 12, 2014
    Publication date: August 27, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shohei Asami, Toshikatsu Hida, Mitsunori Tadokoro, Hirokazu Morita
  • Patent number: 8976589
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first block of the blocks in the nonvolatile memory for the first number of times during a first period. The controller executes writes and erases with respect to other blocks for the second number of times smaller than the first number of times during the first period.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Shohei Asami, Toshikatsu Hida
  • Publication number: 20140281160
    Abstract: According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks. Each erase block includes write blocks. Each of the first storage region and the second storage region includes at least one erase block.
    Type: Application
    Filed: August 2, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Riki Suzuki, Shohei Asami, Toshikatsu Hida, Hiroshi Yao, Kazuhiro Fukutomi
  • Publication number: 20140281144
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Riki SUZUKI, Shohei Asami, Toshikatsu Hida, Hiroshi Yao, Kazuhiro Fukutomi
  • Publication number: 20140269072
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks which store data. Each of the blocks is an erase unit. The controller controls an operation of the nonvolatile memory. The controller executes writes and erases with respect to a first block of the blocks in the nonvolatile memory for the first number of times during a first period. The controller executes writes and erases with respect to other blocks for the second number of times smaller than the first number of times during the first period.
    Type: Application
    Filed: June 24, 2013
    Publication date: September 18, 2014
    Inventors: Riki Suzuki, Shohei Asami, Toshikatsu Hida