Patents by Inventor Shohei Asami
Shohei Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10777283Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.Type: GrantFiled: September 10, 2019Date of Patent: September 15, 2020Assignee: Toshiba Memory CorporationInventors: Shohei Asami, Toshikatsu Hida
-
Patent number: 10770147Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.Type: GrantFiled: March 1, 2017Date of Patent: September 8, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Toshikatsu Hida
-
Patent number: 10719396Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.Type: GrantFiled: February 6, 2019Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Shohei Asami, Yoshihisa Kojima
-
Publication number: 20200211654Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.Type: ApplicationFiled: September 10, 2019Publication date: July 2, 2020Applicant: Toshiba Memory CorporationInventors: Shohei Asami, Toshikatsu Hida
-
Publication number: 20200083240Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Ange SIA, Riki SUZUKI, Shohei ASAMI
-
Publication number: 20200075106Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: March 11, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
-
Patent number: 10529730Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: August 1, 2018Date of Patent: January 7, 2020Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
-
Publication number: 20190286518Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.Type: ApplicationFiled: February 6, 2019Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Shohei ASAMI, Yoshihisa KOJIMA
-
Publication number: 20190094927Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.Type: ApplicationFiled: June 18, 2018Publication date: March 28, 2019Inventors: Yuka KUWANO, Takehiko AMAKI, Toshikatsu HIDA, Shohei ASAMI
-
Publication number: 20190074283Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: August 1, 2018Publication date: March 7, 2019Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa Kojima, Toshikatsu Hida, Marie Sia, Riki Suzuki, Shohei Asami
-
Publication number: 20180091170Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.Type: ApplicationFiled: March 1, 2017Publication date: March 29, 2018Inventors: Shohei ASAMI, Toshikatsu HIDA
-
Patent number: 9891848Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.Type: GrantFiled: September 8, 2015Date of Patent: February 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
-
Patent number: 9875803Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller reads data from third memory cells included in the second memory cells by using the calculated second read voltage.Type: GrantFiled: March 9, 2016Date of Patent: January 23, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Toshikatsu Hida
-
Publication number: 20170076807Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller ads data from third memory cells included in the second memory cells by using the calculated second read voltage.Type: ApplicationFiled: March 9, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shohei ASAMI, Toshikatsu Hida
-
Patent number: 9568987Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.Type: GrantFiled: July 10, 2015Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuru Anazawa, Toshikatsu Hida, Shohei Asami
-
Patent number: 9564930Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.Type: GrantFiled: March 3, 2015Date of Patent: February 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Riki Suzuki, Toshikatsu Hida, Mitsunori Tadokoro, Yoshihisa Kojima, Shohei Asami
-
Publication number: 20160266638Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.Type: ApplicationFiled: July 10, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuru ANAZAWA, Toshikatsu HIDA, Shohei ASAMI
-
Patent number: 9442560Abstract: According to one embodiment, a memory system includes a non-volatile first storage unit, a second storage unit, a third storage unit, and a controller. The controller is configured to selectively execute, following transition to a first mode, either a procedure of writing data of the second storage unit in the third storage unit, or a procedure of writing data of the third storage unit in the first storage unit while reducing power feed to the first and third storage units.Type: GrantFiled: June 12, 2014Date of Patent: September 13, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shohei Asami, Toshikatsu Hida, Mitsunori Tadokoro, Hirokazu Morita
-
Publication number: 20160259576Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.Type: ApplicationFiled: September 8, 2015Publication date: September 8, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shohei ASAMI, Tokumasa HARA, Hiroshi YAO, Kenichiro YOSHII, Riki SUZUKI, Toshikatsu HIDA, Osamu TORII
-
Publication number: 20160072527Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.Type: ApplicationFiled: March 3, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Riki SUZUKI, Toshikatsu HIDA, Mitsunori TADOKORO, Yoshihisa KOJIMA, Shohei ASAMI