Patents by Inventor Shoichi Kabuyanagi
Shoichi Kabuyanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402322Abstract: A semiconductor device according to an embodiment includes a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor. The first oxide semiconductor contacts, at one end, the first conductor, and extends in a first direction intersecting a surface of the first conductor. The first insulator surrounds a side surface of the first oxide semiconductor. The second conductor and the first oxide semiconductor interpose the first insulator therebetween. The third conductor contacts another end of the first oxide semiconductor. The fourth conductor extends in a second direction intersecting the first direction, and contacts a second conductor on a side opposite to the first insulator. The second conductor is of a material with a higher work function than a material of the fourth conductor.Type: ApplicationFiled: March 13, 2023Publication date: December 14, 2023Applicant: Kioxia CorporationInventors: Shoichi Kabuyanagi, Tsuyoshi Sugisaki, Shosuke Fujii
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Patent number: 11672129Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.Type: GrantFiled: January 13, 2021Date of Patent: June 6, 2023Assignee: Kioxia CorporationInventors: Shoichi Kabuyanagi, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
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Publication number: 20210134814Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.Type: ApplicationFiled: January 13, 2021Publication date: May 6, 2021Applicant: Toshiba Memory CorporationInventors: Shoichi Kabuyanagi, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
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Patent number: 10923486Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.Type: GrantFiled: February 26, 2018Date of Patent: February 16, 2021Assignee: Toshiba Memory CorporationInventors: Shoichi Kabuyanagi, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
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Publication number: 20200303461Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.Type: ApplicationFiled: September 9, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shoichi KABUYANAGI, Shosuke FUJII, Masumi SAITOH
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Patent number: 10784312Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.Type: GrantFiled: September 9, 2019Date of Patent: September 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shoichi Kabuyanagi, Shosuke Fujii, Masumi Saitoh
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Patent number: 10692934Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, and a first layer. A direction from the first conductive layer toward the second conductive layer is aligned with a first direction. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region including titanium and oxygen, a second region including aluminum and oxygen and being provided between the first conductive layer and the first region, and a third region including aluminum and oxygen and being provided between the first region and the second conductive layer. A surface area in a first plane of a brookite region included in the first region is 58 percent or more of a surface area in the first plane of the first region. The first plane crosses the first direction.Type: GrantFiled: March 13, 2019Date of Patent: June 23, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Marina Yamaguchi, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20200083292Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, and a first layer. A direction from the first conductive layer toward the second conductive layer is aligned with a first direction. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region including titanium and oxygen, a second region including aluminum and oxygen and being provided between the first conductive layer and the first region, and a third region including aluminum and oxygen and being provided between the first region and the second conductive layer. A surface area in a first plane of a brookite region included in the first region is 58 percent or more of a surface area in the first plane of the first region. The first plane crosses the first direction.Type: ApplicationFiled: March 13, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Marina YAMAGUCHI, Shoichi KABUYANAGI, Masumi SAITOH
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Patent number: 10446749Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.Type: GrantFiled: September 18, 2018Date of Patent: October 15, 2019Assignee: Toshiba Memory CorporationInventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
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Publication number: 20190296234Abstract: A memory device according to an embodiment includes a first conductive layer extending in a first direction, a second conductive layer extending in the first direction, a third conductive layer extending in a second direction intersecting the first direction, an insulating layer containing aluminum oxide provided between the first conductive layer and the second conductive layer, and a first insulating film including a first region located between the first conductive layer and the third conductive layer and a second region located between the insulating layer and the third conductive layer. The first region includes hafnium oxide mainly formed as an orthorhombic. The second region includes hafnium oxide mainly formed as crystals other than the orthorhombic.Type: ApplicationFiled: September 18, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Yoko Yoshimura, Hiromichi Kuriyama, Shoichi Kabuyanagi, Yuuichi Kamimuta, Chika Tanaka, Masumi Saitoh
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Patent number: 10249818Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: GrantFiled: March 6, 2018Date of Patent: April 2, 2019Assignee: Toshiba Memory CorporationInventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20190088870Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.Type: ApplicationFiled: March 6, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Marina YAMAGUCHI, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
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Publication number: 20190088664Abstract: A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.Type: ApplicationFiled: February 26, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Shoichi KABUYANAGI, Yuuichi Kamimuta, Masumi Saitoh, Marina Yamaguchi
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Patent number: 10050087Abstract: A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.Type: GrantFiled: September 8, 2017Date of Patent: August 14, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shoichi Kabuyanagi, Masumi Saitoh, Marina Yamaguchi, Takashi Tachikawa