Patents by Inventor Shoichi KUGA
Shoichi KUGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11256171Abstract: A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.Type: GrantFiled: November 2, 2018Date of Patent: February 22, 2022Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Nakamura, Shinya Soneda, Shoichi Kuga
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Patent number: 11145712Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.Type: GrantFiled: April 24, 2017Date of Patent: October 12, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Tetsu Negishi, Shoichi Kuga
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Publication number: 20200058733Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.Type: ApplicationFiled: April 24, 2017Publication date: February 20, 2020Applicant: Mitsubishi Electric CorporationInventors: Tetsu NEGISHI, Shoichi KUGA
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Patent number: 10468314Abstract: A semiconductor power module includes: an insulating substrate including a concave portion provided on a top surface of the insulating substrate; a substrate electrode embedded in the concave portion; a semiconductor device bonded onto the substrate electrode; and an insulating resin covering a top end part of the substrate electrode.Type: GrantFiled: October 23, 2017Date of Patent: November 5, 2019Assignee: Mitsubishi Electric CorporationInventor: Shoichi Kuga
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Publication number: 20190243245Abstract: A film resist is a member for being bonded to a main surface of a substrate, which main surface is provided with a mark. The film resist includes a cutout for the mark to be checked.Type: ApplicationFiled: November 2, 2018Publication date: August 8, 2019Applicant: Mitsubishi Electric CorporationInventors: Hiroyuki NAKAMURA, Shinya SONEDA, Shoichi KUGA
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Patent number: 10073360Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.Type: GrantFiled: January 28, 2015Date of Patent: September 11, 2018Assignee: Mitsubishi Electric CorporationInventors: Naoyuki Takeda, Shoichi Kuga
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Publication number: 20180254228Abstract: A semiconductor power module includes: an insulating substrate including a concave portion provided on a top surface of the insulating substrate; a substrate electrode embedded in the concave portion; a semiconductor device bonded onto the substrate electrode; and an insulating resin covering a top end part of the substrate electrode.Type: ApplicationFiled: October 23, 2017Publication date: September 6, 2018Applicant: Mitsubishi Electric CorporationInventor: Shoichi KUGA
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Patent number: 9899189Abstract: A technique disclosed in the present specification relates to an ion implanter capable of preventing a semiconductor substrate from being damaged by an abnormal electric discharge through a simple method. The ion implanter of this technique includes an ion irradiation unit configured to irradiate a surface of a semiconductor substrate with ions. The ion implanter also includes at least one electrode (needle electrode, annular electrode) disposed in a position in the vicinity of at least one of back and side surfaces of an end of the semiconductor substrate. The position is dischargeable to and from the semiconductor substrate. The at least one electrode (needle electrode, annular electrode) is spaced apart from the semiconductor substrate.Type: GrantFiled: July 11, 2016Date of Patent: February 20, 2018Assignee: Mitsubishi Electric CorporationInventor: Shoichi Kuga
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Publication number: 20180024437Abstract: An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.Type: ApplicationFiled: January 28, 2015Publication date: January 25, 2018Applicant: Mitsubishi Electric CorporationInventors: Naoyuki TAKEDA, Shoichi KUGA
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Patent number: 9760007Abstract: A semiconductor device manufacturing method of the present invention includes a coating step of coating a front surface of a wafer with a material containing a solvent, a volatilization step of volatilizing the solvent by heating the material, and a rinse step of jetting an edge rinse solution for removing the material from a first nozzle to a peripheral portion of the front surface of the wafer while rotating the wafer.Type: GrantFiled: February 13, 2014Date of Patent: September 12, 2017Assignee: Mitsubishi Electric CorporationInventor: Shoichi Kuga
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Publication number: 20170207080Abstract: A semiconductor device manufacturing method of the present invention includes a coating step of coating a front surface of a wafer with a material containing a solvent, a volatilization step of volatilizing the solvent by heating the material, and a rinse step of jetting an edge rinse solution for removing the material from a first nozzle to a peripheral portion of the front surface of the wafer while rotating the wafer.Type: ApplicationFiled: February 13, 2014Publication date: July 20, 2017Applicant: Mitsubishi Electric CorporationInventor: Shoichi KUGA
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Publication number: 20170178860Abstract: A technique disclosed in the present specification relates to an ion implanter capable of preventing a semiconductor substrate from being damaged by an abnormal electric discharge through a simple method. The ion implanter of this technique includes an ion irradiation unit configured to irradiate a surface of a semiconductor substrate with ions. The ion implanter also includes at least one electrode (needle electrode, annular electrode) disposed in a position in the vicinity of at least one of back and side surfaces of an end of the semiconductor substrate. The position is dischargeable to and from the semiconductor substrate. The at least one electrode (needle electrode, annular electrode) is spaced apart from the semiconductor substrate.Type: ApplicationFiled: July 11, 2016Publication date: June 22, 2017Applicant: Mitsubishi Electric CorporationInventor: Shoichi KUGA
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Patent number: 8778133Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.Type: GrantFiled: December 14, 2012Date of Patent: July 15, 2014Assignee: Mitsubishi Electric CorporationInventor: Shoichi Kuga
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Publication number: 20130098542Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.Type: ApplicationFiled: December 14, 2012Publication date: April 25, 2013Inventor: Shoichi KUGA
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Publication number: 20110220296Abstract: A method of peeling a protective tape, includes the steps of mounting a wafer on a stage, the wafer having the protective tape adhered thereto so that the protective tape overlaps only a portion of a notch of the wafer, attaching a peeling adhesive tape to the protective tape, projecting a lift pin from the stage so that the portion of the protective tape which overlaps the notch is raised by a top surface of the lift pin, and with the protective tape raised by the lift pin, pulling the peeling adhesive tape so as to peel the protective tape from the wafer. The top surface of the lift pin has a shape that allows the top surface to raise the portion of the protective tape which overlaps the notch.Type: ApplicationFiled: December 28, 2010Publication date: September 15, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shoichi KUGA