Patents by Inventor Shoichi Ozeki

Shoichi Ozeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6580108
    Abstract: An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: June 17, 2003
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Tomoyuki Utsumi, Shoichi Ozeki, Koichi Suda
  • Patent number: 6040827
    Abstract: A driver circuit wherein a first switching element and a second switching element are totem-pole-connected, wherein the totem pole connection is connected at its one end, node and other end with a power source, an output to a load and a reference potential, respectively, wherein the first switching element is connected between the one end and the node, wherein the second switching element is connected between the node and the other end, and wherein a third switching element is connected between the one end of the totem pole connection and the control terminal of the first switching element.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: March 21, 2000
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Kazuhiro Shiina, Koji Kawamoto, Masato Miura, Hitoshi Ohura, Shoichi Ozeki, Noboru Akiyama, Kunihoro Nunomura, Minehiro Nemoto, Masahiro Iwamura
  • Patent number: 5818281
    Abstract: For a semiconductor circuit having one or more semiconductor devices, such as an IGBT, a turn-ON prevention circuit is provided for each device which prevents the device from turning ON during OFF times thereof, due to the presence of a transient voltage (dV/dt) across the main terminals of the device. In accordance with such a scheme, a MOSFET is connected between the insulated-gate electrode and emitter of the IGBT, and a capacitor, for example, is connected between the gate of the MOSFET and a sufficient electric potential to thereby effect a temporary turn-ON of the MOSFET to remove parasitic charge build-up in the IGBT before such charge build-up has reached a potential of the turn-ON threshold of the IGBT during OFF times of the IGBT. The capacitance element can be constituted by a MOSFET, namely, the capacitance across the gate-to-drain of an additional MOSFET.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: October 6, 1998
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co.,Ltd.
    Inventors: Hitoshi Ohura, Koji Kawamoto, Shoichi Ozeki
  • Patent number: 5184272
    Abstract: A switching circuit providing detection circuit for detecting a current which flows through a main P-channel MOSFET detection of a floating voltage dependent upon a power supply potential, a reference-voltage generating circuit for generating a reference voltage which is a floating voltage dependent upon the power supply potential and has a constant value independently of variations in power supply potential, a comparator circuit operated on a supply voltage which is a floating voltage dependent upon the power supply potential, for comparing a detected voltage from the detection circuit with the reference voltage from the reference-voltage generating means, to convert the detected voltage into a logic voltage signal (i.e., a bi-level voltage signal and a conversion circuit for converting the logic voltage outputted by the comparator circuit into a voltage measured from a ground potential.
    Type: Grant
    Filed: March 29, 1990
    Date of Patent: February 2, 1993
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor Ltd.
    Inventors: Koichi Suda, Hitoshi Matsuzaki, Masayuki Wada, Shoichi Ozeki
  • Patent number: 4665505
    Abstract: A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: May 12, 1987
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor Ltd.
    Inventors: Nobuaki Miyakawa, Yoshiaki Yazawa, Shoichi Ozeki, Kinya Mitsumoto