Abstract: In a CDMA mobile communications device, a long code generator can be eliminated from a receiving section by storing a received long code at an output timing of a decimating section 11 through calculation of a write address of a FIFO buffer 12a, calculating a read address of the FIFO buffer at the cycle of a reference clock signal output from a reference clock signal generation section 12c, controlling the received long code through use of a FIFO buffer control section 12b which reads the received long code, and by a symbol combining section 10 combining symbols received over paths and output from a RAKE receiving section at the cycle of the reference clock signal and demodulating the combined symbol through use of the received long code.

Abstract: A first station can communicate with a second station by radio. The second station has a function of repeating a received radio signal. A radio communication apparatus in the first station includes a first device for transmitting a first radio-frequency signal containing a predetermined pseudo-noise code signal toward the second station. In the radio communication apparatus, detection is made as to a first timing at which the first device transmits the first radio-frequency signal. A second radio-frequency signal is received by the radio communication apparatus after the first device transmits the first radio-frequency signal. The second radio-frequency signal is converted into a baseband signal. A memory stors the predetermined pseudo-noise code signal. Calculation is made as to a correlation between the baseband signal and the predetermined pseudo-noise code signal stored in the memory. A second timing at which the calculated correlation peaks substantially is detected.

Abstract: A mobile communication receiver of a spread spectrum communication system has a plurality of fingers, a synthesizer for synthesizing data reproduced by the fingers, a power measurement unit for measuring power of reproduction output of the fingers and total power thereof, a error detection unit for detecting an error of output data of the synthesizer, and a control unit for controlling power on and off of the fingers based on the measurement result of the power measurement unit and the error detection result of the error detection means. Power consumption can be reduced in the range in which an error increase does not result.

Abstract: An input bit sequence is converted into n-bit parallel symbol signals each representing one symbol. A shift register stores an "m" number of the n-bit parallel symbol signals, shifting the n-bit parallel symbol signals one symbol by one symbol and outputting them. At least one selector is operative for sequentially selecting one of the k-th symbol signal and the (m+1)-k-th symbol signal outputted by the shift register in response to a clock signal, where k equals 1, 2, . . . , (m-1)/2. A sampling counter serves to count pairs of successive clock pulses of the clock signal. An Exclusive-OR circuit executes Exclusive-OR operation between the clock signal and an output signal of the sampling counter. At least one first read-only memory stores data representing portions of predetermined impulse response waveforms, and outputs the data in response to an address signal having higher and lower parts.