Patents by Inventor Shoji Mizuno

Shoji Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11356076
    Abstract: In a surface acoustic wave filter according to an embodiment, a thickness of a piezoelectric crystal substrate bonded over a support substrate made of an oxide crystal is 0.05 to 0.5 ?m, and an odd-order harmonic is used.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: June 7, 2022
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Kazuhito Kishida, Shoji Kakio, Jun Mizuno
  • Patent number: 10446649
    Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 15, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomoo Morino, Shoji Mizuno, Yuichi Takeuchi, Akitaka Soeno, Yukihiko Watanabe
  • Publication number: 20190288107
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Inventors: Hirotaka SAIKAKU, Jun SAKAKIBARA, Shoji MIZUNO, Yuichi TAKEUCHI
  • Patent number: 10388527
    Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 20, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Norihiro Togawa, Narumasa Soejima, Shoji Mizuno
  • Patent number: 10374079
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 6, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Saikaku, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 10153345
    Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: December 11, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Shoji Mizuno, Yukihiko Watanabe, Sachiko Aoi
  • Patent number: 10128344
    Abstract: A semiconductor device includes: a drain region made of a first or second conductivity type semiconductors; a drift layer made of the first conductivity type semiconductor; a base region made of the second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity semiconductor with higher concentration; a trench gate structure having upper and lower gate structures; a source electrode connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The upper gate structure is inside the trench at an upper side, and includes a first gate insulation film and a first gate electrode. The lower gate structure is inside the trench at a lower side, and includes a second gate insulation film made of higher dielectric insulation material and a second gate electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 13, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomohiro Mimura, Takashi Kanemura, Shoji Mizuno, Masahiro Sugimoto, Sachiko Aoi
  • Patent number: 10068972
    Abstract: A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first conductive type, wherein the drift region is in contact with the trench gate; a body region of a second conductive type, wherein the body region is disposed above the drift region and is in contact with the trench gate; a source region of the first conductive type, wherein the source region is disposed above the body region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate; and a front surface region of the second conductive type, wherein the front surface region is disposed above the source region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Sachiko Aoi, Shoji Mizuno, Shinichiro Miyahara
  • Publication number: 20180175149
    Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
    Type: Application
    Filed: June 3, 2016
    Publication date: June 21, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi TAKAYA, Shoji MIZUNO, Yukihiko WATANABE, Sachiko AOI
  • Publication number: 20180144938
    Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.
    Type: Application
    Filed: October 6, 2017
    Publication date: May 24, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Norihiro TOGAWA, Narumasa SOEJIMA, Shoji MIZUNO
  • Publication number: 20180114845
    Abstract: A semiconductor device includes: a drain region made of a first or second conductivity type semiconductors; a drift layer made of the first conductivity type semiconductor; a base region made of the second conductivity type semiconductor; a source region made of the first conductivity type semiconductor with higher concentration; a contact region made of the second conductivity semiconductor with higher concentration; a trench gate structure having upper and lower gate structures; a source electrode connected to the source and contact regions; and a drain electrode at a rear side of the drain region. The upper gate structure is inside the trench at an upper side, and includes a first gate insulation film and a first gate electrode. The lower gate structure is inside the trench at a lower side, and includes a second gate insulation film made of higher dielectric insulation material and a second gate electrode.
    Type: Application
    Filed: March 10, 2016
    Publication date: April 26, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomohiro MIMURA, Takashi KANEMURA, Shoji MIZUNO, Masahiro SUGIMOTO, Sachiko AOI
  • Patent number: 9954073
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: April 24, 2018
    Assignee: DENSO CORPORATION
    Inventors: Nozomu Akagi, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 9871098
    Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 16, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Atsushi Onogi, Sachiko Aoi, Shoji Mizuno
  • Patent number: 9818856
    Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 14, 2017
    Assignee: DENSO CORPORATION
    Inventors: Shinichi Hoshi, Shoji Mizuno, Tetsu Kachi, Tsutomu Uesugi, Kazuyoshi Tomita, Kenji Ito
  • Publication number: 20170288014
    Abstract: A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 5, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Atsushi ONOGI, Sachiko AOI, Shoji MIZUNO
  • Publication number: 20170263757
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 14, 2017
    Inventors: Hirotaka SAIKAKU, Jun SAKAKIBARA, Shoji MIZUNO, Yuichi TAKEUCHI
  • Patent number: 9660046
    Abstract: A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 23, 2017
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Sachiko Aoi, Yukihiko Watanabe, Katsumi Suzuki, Shoji Mizuno
  • Patent number: 9640651
    Abstract: A semiconductor device includes a termination trench surrounding a region in which a plurality of gate trenches is provided; a p-type lower end region being in contact with a lower end of the termination trench; a p-type outer circumference region being in contact with the termination trench from an outer circumferential side and exposed on a surface of the semiconductor device; a plurality of guard ring regions of a p-type provided on an outer circumferential side of the p-type outer circumference region and exposed on the surface; and an n-type outer circumference region separating the p-type outer circumference region from the guard ring regions and separating the guard ring regions from each another.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 2, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Kimimori Hamada, Shoji Mizuno, Sachiko Aoi, Yukihiko Watanabe
  • Publication number: 20170012108
    Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Jun SAKAKIBARA, Nozomu AKAGI, Shoji MIZUNO, Yuichi TAKEUCHI, Katsumi SUZUKI
  • Publication number: 20170012109
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Nozomu AKAGI, Jun SAKAKIBARA, Shoji MIZUNO, Yuichi TAKEUCHI