Patents by Inventor Shoko Omizo

Shoko Omizo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8796076
    Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Patent number: 8659137
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20130334709
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoko OMIZO, Atsushi YOSHIMURA, Fumihiro IWAMI
  • Patent number: 8557635
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20130062782
    Abstract: After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 14, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Publication number: 20120223441
    Abstract: In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.
    Type: Application
    Filed: February 23, 2012
    Publication date: September 6, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoko OMIZO, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 7955896
    Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: June 7, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Patent number: 7849897
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20100035381
    Abstract: A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (?0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (?0.5 rpm/?5 rpm) of the viscosity (?0.5 rpm) at the low-rotation speed to a viscosity (?5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.
    Type: Application
    Filed: July 24, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Yoshimura, Shoko Omizo
  • Publication number: 20080110546
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Application
    Filed: August 24, 2007
    Publication date: May 15, 2008
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20070292989
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Application
    Filed: July 19, 2007
    Publication date: December 20, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Mikio Matsui
  • Patent number: 7276784
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Mikio Matsui
  • Publication number: 20060079020
    Abstract: A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members isolated from the first semiconductor chip, electrically connecting to the first substrate with the base substrate; and a first encapsulating layer provided around the first connection members.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 13, 2006
    Inventors: Shoko Omizo, Mikio Matsui
  • Patent number: 6686222
    Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: February 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mikio Matsui, Takao Sato
  • Publication number: 20020187588
    Abstract: In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.
    Type: Application
    Filed: May 17, 2002
    Publication date: December 12, 2002
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mikio Matsui, Takao Sato
  • Patent number: 6400037
    Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (Rmax: 0.5 to 5 &mgr;m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: June 4, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoko Omizo
  • Patent number: 6261919
    Abstract: A mark of a semiconductor device is formed of a molten trace obtained by selectively applying a laser to a ground back surface of a semiconductor substrate. Since the molten trace mark is formed in a form of a planarized surface on a back surface of a wafer or a chip which has been rendered uneven by grinding, visual recognition of the mark can be improved. Furthermore, since the mark is not deeply inscribed into the wafer or the chip, unlike the case of a dot mark, it is possible to maintain a die strength at a high level. In particular, when the molten trace mark is formed by using SHG-YAG laser, it is possible to suppress the depth of the layer from being thermally influenced, up to about several &mgr;m. As a result, it is possible to suppress thermal influence upon the inner circuit formed in a silicon chip and wiring formed therein.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: July 17, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoko Omizo
  • Patent number: 6143587
    Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (R.sub.max :0.5 to 5 .mu.m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: November 7, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoko Omizo