Patents by Inventor Shosaku Yamanaka

Shosaku Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5640669
    Abstract: A process for preparing a metallic porous body, comprising: forming a layer comprising Cu, a Cu alloy, or a precursor thereof onto a skeleton composed of a porous resin body having a three-dimensional network, heat-treating the resin body with the layer formed thereon to remove a heat-decomposable organic component, thereby forming a porous metallic skeleton of Cu or a Cu alloy; and plating the surface of the Cu or Cu alloy skeleton with Ni or an Ni alloy. The heat treating may be carried out by direct induction heating. The metallic porous body is useful as electrodes for batteries, various filters, carriers for catalysts, etc. When the porous body is cut and used as the electrode substrate, the coating of an area, where Cu or its alloy has been exposed by cutting or the like, with a third metal having a lower ionization tendency than Cu or its alloy can provide an electrode substrate having better corrosion resistance and battery service life.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: June 17, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keizo Harada, Masayuki Ishii, Kenichi Watanabe, Shosaku Yamanaka
  • Patent number: 5597665
    Abstract: A porous metal body is produced by forming a coating film of one or more metal capable of forming a eutectic alloy at temperatures not higher than the melting point of Al on a foamed resin skeleton having a three-dimensional network structure according to the plating, vapor deposition, sputtering, CVD or other vapor phase process, impregnating the foamed resin having the coating film formed thereon with a paste comprising powdery Al, a binder and an organic solvent as principal components to thereby obtain a paste-coated composite and heating the composite at a temperature ranging from 550.degree. C. to 750.degree. C. in a nonoxidizing atmosphere. The resultant porous metal body has a large effective surface area and a high space utilization factor and exhibits excellent performance in uses in filters and battery plates.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: January 28, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keizo Harada, Masayuki Ishii, Shosaku Yamanaka
  • Patent number: 5556807
    Abstract: A method and resulting structure for constructing an IC package utilizing thin film technology. The package has a bottom conductive plate that has a layer of ceramic vapor deposited onto the plate in a predetermined pattern. Adjacent to the insulative layer of ceramic is a layer of conductive metal vapor deposited onto the ceramic. The layer of metal can be laid down onto the ceramic in a predetermined pattern to create a power plane, a plurality of signal lines, or a combination of power planes and signal lines. On top of the layer of conductive material is a lead frame separated by a layer of insulative polyimide material. The polyimide material has a plurality of holes filled with a conductive material, which electrically couple the layer of conductive material with the leads of the lead frame.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Debendra Mallik, Syunsuke Ban, Takatoshi Takikawa, Shosaku Yamanaka
  • Patent number: 5455453
    Abstract: A plastic package type semiconductor device is composed of a rolled metal substrate made of copper or copper alloy and an insulating film formed on the surface of the substrate. The film may be a single-layer film made of silicon oxynitride or a composite film formed by laminating a silicon oxide layer and a silicon oxynitride layer (or a silicon nitride layer). A semiconductor element is mounted on the film or on the exposed surface of the substrate. Other passive elements are provided on the film. After connecting these elements with bonding wires, the entire device is sealed in a resin molding. This device is thus free of cracks due to difference in thermal expansion between the film and the substrate, or peeling due to moisture absorption.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: October 3, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keizo Harada, Takao Maeda, Takatoshi Takikawa, Shunsuke Ban, Shosaku Yamanaka
  • Patent number: 5369220
    Abstract: A wiring board has a wiring circuit which is reliable and which can be easily miniaturized, and used for the production of a highly integrated, lighter, thinner, shorter, smaller and low-cost semiconductor device. This wiring board can be sealed in a plastic package. The wiring board has a metal plate and a thin-film dielectric layer formed on the surface of the metal plate. A semiconductor device is mounted on the surface of the dielectric layer or the exposed surface of the metal plate. Film wirings are formed on the dielectric layer. Each film wiring is in the form of a laminate formed by laminating, by vapor phase deposition or by plating, a an aluminum conductive layer, an adhesive layer of chromium, titanium or a laminate thereof, a diffusion barrier layer of nickel, copper or a laminate thereof, and a corrosion-preventive and wire bonding layer of gold.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: November 29, 1994
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Keizo Harada, Takatoshi Takikawa, Takao Maeda, Shunsuke Ban, Shosaku Yamanaka
  • Patent number: 5356661
    Abstract: A heat transfer insulated part including a heat transfer substrate formed of a sintered metal of Cu-W or Cu-Mo, an insulating ceramic layer for electrically insulating the heat transfer substrate, formed of ceramic such as Al.sub.2 O.sub.3, SiO.sub.2 and Si.sub.3 N.sub.4, and a barrier layer provided between the heat transfer substrate and an insulating ceramic layer composed of at least either one of metal layers of W and Mo. Furthermore, preferably, an intermediate layer composed of titanium carbide and/or titanium nitride and so forth for enhancing the adhesive property between the insulating ceramic layer and the barrier layer is provided.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: October 18, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akira Doi, Shosaku Yamanaka, Hiromu Kawai
  • Patent number: 5353499
    Abstract: A method of forming a multilayered wiring board having a multilayered wiring structure includes the steps of forming a first mesh wiring layer having a plurality of holes therein, and forming a second wiring layer having a plurality of wirings undulating up and down so as to descend into the holes formed in the first wiring layer. In another method, the first wiring layer is formed with a plurality of protrusions and the wirings of the second wiring layer are formed between the protrusions. In the wiring boards formed according to the methods of the present invention, crosstalk between the wirings is suppressed.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: October 11, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hisao Hattori, Tomohiko Ihara, Hiroshi Yoshino, Shosaku Yamanaka
  • Patent number: 5348792
    Abstract: This multilayered wiring board having a multilayered wiring structure includes a first mesh wiring layer having a plurality of holes therein, and a second wiring layer having a plurality of wirings. The wirings of the second wiring layer undulate up and down so as to descend towards the holes formed in the first wiring layer. In another arrangement, the first wiring layer has a plurality of protrusions protruding toward the second wiring layer at locations between adjacent ones of the wirings of the second wiring layer. In these wiring boards, crosstalk between the wirings is suppressed.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: September 20, 1994
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hisao Hattori, Tomohiko Ihara, Hiroshi Yoshino, Shosaku Yamanaka
  • Patent number: 5134459
    Abstract: A lead frame for a high-density, sealed type of semiconductor device having many input/output pins and capable of high-speed operation is made of a magnetic material with a covering layer of a non-magnetic metal. The covering layer covers a top surface, a bottom surface, both side surfaces and an inner end face of a portion of the leads of the lead frame which is to be sealed in a semiconductor package. The covering layer has a thickness of 1 micron or more at both side surfaces of each lead. Therefore, the inductance at the leads can be reduced remarkably. Thus, the semiconductor can be operated at a high speed with improved reliability.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: July 28, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Maeda, Tomohiko Ihara, Masaharu Yasuhara, Shosaku Yamanaka