Patents by Inventor Shouli Yan
Shouli Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9874887Abstract: A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.Type: GrantFiled: February 24, 2012Date of Patent: January 23, 2018Assignee: Silicon Laboratories Inc.Inventors: Shouli Yan, Alan Westwick
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Patent number: 9742397Abstract: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.Type: GrantFiled: November 30, 2015Date of Patent: August 22, 2017Assignee: Silicon Laboratories Inc.Inventors: Gang Yuan, Shouli Yan, Matthew Powell
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Publication number: 20170155386Abstract: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Inventors: Gang Yuan, Shouli Yan, Matthew Powell
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Patent number: 9625925Abstract: A method includes using a pass device of a linear regulator to provide an output signal to an output of the linear regulator in response to a signal that is received at a control terminal of the pass device. The method includes using the linear regulator to regulate the signal received at the control terminal based at least in part on the output signal; and controlling a closed loop frequency response of the linear regulator to cause a direct current (DC) gain of the linear regulator to extend to a frequency near or at frequency of a zero that is associated with a decoupling capacitor that is coupled to the output of the linear regulator.Type: GrantFiled: November 24, 2014Date of Patent: April 18, 2017Assignee: Silicon Laboratories Inc.Inventors: Shouli Yan, Axel Thomsen, Praveen Kallam
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Patent number: 9614528Abstract: In an embodiment, an apparatus may include an amplifier circuit including a first input to receive a signal, a second input to receive a feedback signal, and an output. The apparatus may further include a buffer circuit including an input coupled to the output of the amplifier and including an output coupled to an output node. The apparatus may also include a feedback circuit coupled between the output node and the second input of the amplifier circuit. The feedback circuit may include at least one non-linear resistor configured to define a feedback ratio that changes in response to a voltage at the output node.Type: GrantFiled: December 6, 2014Date of Patent: April 4, 2017Assignee: Silicon Laboratories Inc.Inventors: Mohamed Mostafa Elsayed, Shouli Yan
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Patent number: 9576679Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.Type: GrantFiled: October 9, 2014Date of Patent: February 21, 2017Assignee: Silicon Laboratories Inc.Inventors: Matthew R Powell, Shouli Yan
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Publication number: 20160164522Abstract: In an embodiment, an apparatus may include an amplifier circuit including a first input to receive a signal, a second input to receive a feedback signal, and an output. The apparatus may further include a buffer circuit including an input coupled to the output of the amplifier and including an output coupled to an output node. The apparatus may also include a feedback circuit coupled between the output node and the second input of the amplifier circuit. The feedback circuit may include at least one non-linear resistor configured to define a feedback ratio that changes in response to a voltage at the output node.Type: ApplicationFiled: December 6, 2014Publication date: June 9, 2016Applicant: Silicon Laboratories Inc.Inventors: Mohamed Mostafa Elsayed, Shouli Yan
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Publication number: 20160147239Abstract: A method includes using a pass device of a linear regulator to provide an output signal to an output of the linear regulator in response to a signal that is received at a control terminal of the pass device. The method includes using the linear regulator to regulate the signal received at the control terminal based at least in part on the output signal; and controlling a closed loop frequency response of the linear regulator to cause a direct current (DC) gain of the linear regulator to extend to a frequency near or at frequency of a zero that is associated with a decoupling capacitor that is coupled to the output of the linear regulator.Type: ApplicationFiled: November 24, 2014Publication date: May 26, 2016Inventors: Shouli Yan, Axel Thomsen, Praveen Kallam
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Publication number: 20160104543Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.Type: ApplicationFiled: October 9, 2014Publication date: April 14, 2016Applicant: Silicon Laboratories Inc.Inventors: Matthew R. Powell, Shouli Yan
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Patent number: 9041584Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.Type: GrantFiled: September 3, 2013Date of Patent: May 26, 2015Assignee: Silicon Laboratories Inc.Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
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Patent number: 9041569Abstract: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.Type: GrantFiled: June 28, 2013Date of Patent: May 26, 2015Assignee: Silicon Laboratories Inc.Inventors: Yan Zhou, Clayton Daigle, Shouli Yan, Mohamed Elsayed
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Publication number: 20150061913Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: Silicon Laboratories Inc.Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
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Patent number: 8952839Abstract: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.Type: GrantFiled: December 31, 2012Date of Patent: February 10, 2015Assignee: Silicon Laboratories Inc.Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen, Jinwen Xiao
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Publication number: 20150002321Abstract: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Yan Zhou, Clayton Daigle, Shouli Yan, Mohamed Elsayed
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Patent number: 8922418Abstract: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.Type: GrantFiled: May 10, 2013Date of Patent: December 30, 2014Assignee: Silicon Laboratories Inc.Inventors: Mohamed Elsayed, Xiaodong Wang, Shouli Yan
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Publication number: 20140333465Abstract: A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Inventors: Mohamed Elsayed, Xiaodong Wang, Shouli Yan
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Publication number: 20140184435Abstract: A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen, Jinwen Xiao
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Publication number: 20130221940Abstract: A technique includes using a pass device of a linear regulator to provide an output signal for the linear regulator in response to a signal that is received at a control terminal of the pass device. The control terminal is coupled to a node, and the node is associated with a bias current. The technique includes using a feedback path to communicate a feedback current with the node to regulate the output signal. The use of the feedback path includes regulating a magnitude of the feedback current to be within a range of magnitudes, which include a magnitude that exceeds a magnitude of the bias current.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Inventors: Shouli Yan, Dazhi Wei, Alan L. Westwick
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Publication number: 20130221937Abstract: A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.Type: ApplicationFiled: February 24, 2012Publication date: August 29, 2013Inventors: Shouli Yan, Alan Westwick
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Patent number: 8384573Abstract: A digital-to-analog converter (DAC) with a digital segment having a digital data input and an analog segment coupled to the digital segment and having an analog output to output an analog signal corresponding to the digital data. The analog segment includes one or more gain stages and a feedback structure to couple the analog output to the one or more gain stages to attenuate signal distortion at the analog output. A combined gain of the one or more gain stages determines a signal distortion attenuation characteristic of the analog segment.Type: GrantFiled: May 16, 2008Date of Patent: February 26, 2013Assignee: Intellectual Ventures Holding 40 LLCInventors: Xiaohong Li, Shouli Yan, Zhiheng Cao