Patents by Inventor Shrikar Bhagath
Shrikar Bhagath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830849Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.Type: GrantFiled: November 4, 2021Date of Patent: November 28, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Saurabh Nilkanth Athavale, Shrikar Bhagath, Pradeep Rai
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Publication number: 20230328910Abstract: A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Bo Yang, Warren Middlekauff, Sean Lau, Ning Ye, Shrikar Bhagath, Yangming Liu
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Publication number: 20230137512Abstract: A semiconductor memory device, also referred to as a solid state drive, includes thermally conductive components such as a conductive coating to draw heat away from the semiconductive package. The coating may also be electrically conductive to provide shielding from and absorption of electromagnetic interference. In examples, a semiconductor device including a substrate may be affixed to an edge connector printed circuit board with solder balls to form a solid state drive. In further examples, the substrate may be omitted, and semiconductor memory dies, a controller die and other electronic components may be directly surface mounted to an edge connector printed circuit board to form a solid state drive.Type: ApplicationFiled: November 3, 2021Publication date: May 4, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Hui Xu, Kim Lee Bock, Rama Shukla, Chong Un Tan, Yoong Tatt Chin, Shrikar Bhagath
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Publication number: 20230133965Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Applicant: Western Digital Technologies, Inc.Inventors: Saurabh Nilkanth Athavale, Shrikar Bhagath, Pradeep Rai
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Patent number: 11551991Abstract: A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.Type: GrantFiled: June 5, 2020Date of Patent: January 10, 2023Assignee: Western Digital Technologies, Inc.Inventors: Bo Yang, Chun Sean Lau, Ning Ye, Shrikar Bhagath
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Patent number: 11552040Abstract: A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.Type: GrantFiled: July 21, 2020Date of Patent: January 10, 2023Assignee: Western Digital Technologies, Inc.Inventors: Siqi Zhang, Xu Wang, Pradeep Rai, Shrikar Bhagath
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Publication number: 20220293195Abstract: A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.Type: ApplicationFiled: March 12, 2021Publication date: September 15, 2022Inventors: Shrikar Bhagath, Dean Jenkins, Hedan Zhang, Bret Winkler, Ning Ye
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Publication number: 20220028819Abstract: A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Applicant: Western Digital Technologies, Inc.Inventors: Siqi ZHANG, Xu WANG, Pradeep RAI, Shrikar BHAGATH
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Publication number: 20210384099Abstract: A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.Type: ApplicationFiled: June 5, 2020Publication date: December 9, 2021Applicant: Western Digital Technologies, Inc.Inventors: Bo Yang, Chun Sean Lau, Ning Ye, Shrikar Bhagath
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Patent number: 11094674Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.Type: GrantFiled: March 12, 2020Date of Patent: August 17, 2021Assignee: SanDisk Technologies LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Rama Shukla
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Patent number: 11011500Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.Type: GrantFiled: March 12, 2020Date of Patent: May 18, 2021Assignee: SanDisk Technologies LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Chih Yang Li, Srinivasan Sivaram, Rama Shukla
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Publication number: 20210104495Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.Type: ApplicationFiled: March 12, 2020Publication date: April 8, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Chih Yang Li, Srinivasan Sivaram, Rama Shukla
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Publication number: 20210104494Abstract: A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.Type: ApplicationFiled: March 12, 2020Publication date: April 8, 2021Applicant: SANDISK TECHNOLOGIES LLCInventors: Nagesh Vodrahalli, Shrikar Bhagath, Rama Shukla
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Patent number: 10290354Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.Type: GrantFiled: October 31, 2017Date of Patent: May 14, 2019Assignee: SanDisk Technologies LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj, Sukhminder Singh Lobana, Shrikar Bhagath
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Publication number: 20190130978Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Daniel Linnen, Srikar Peesari, Kirubakaran Periyannan, Avinash Rajagiri, Shantanu Gupta, Jagdish Sabde, Ashish Ghai, Deepak Bharadwaj, Sukhminder Singh Lobana, Shrikar Bhagath
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Patent number: 10128218Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.Type: GrantFiled: June 22, 2017Date of Patent: November 13, 2018Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
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Publication number: 20180175006Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.Type: ApplicationFiled: June 22, 2017Publication date: June 21, 2018Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
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Publication number: 20150214184Abstract: A system and method are disclosed for applying a die attach epoxy to substrates on a panel of substrates. The system includes a window clamp having one or more windows through which the epoxy may be applied onto the substrate panel. The size and shape of the one or more windows correspond to the size and shape of the area on the substrate to receive the die attach epoxy. Once the die attach epoxy is sprayed onto the substrate through the windows of the window clamp, the die may be affixed to the substrate and the epoxy cured in one or more curing steps. The system may further include a clean-up follower for cleaning epoxy off of the window clamp, and a window cleaning mechanism for cleaning epoxy off of the sidewalls of the windows of the window clamp.Type: ApplicationFiled: April 9, 2015Publication date: July 30, 2015Applicants: SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD., SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.Inventors: Wei Gu, Zhong Lu, Shrikar Bhagath, Chin-Tien Chiu, Hem Takiar, XiangYang Liu
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Patent number: 9064836Abstract: A semiconductor wafer, die and semiconductor package formed therefrom are disclosed, where the inactive surface of the wafer has an extrinsic gettering pattern formed from a texturing process. In examples, the texturing process follows a polishing process that removes stress concentration point from the inactive surface of the wafer.Type: GrantFiled: August 9, 2010Date of Patent: June 23, 2015Assignee: SanDisk Semiconductor (Shanghai) Co., Ltd.Inventors: Chin-Tien Chiu, Shrikar Bhagath, Yuang Zhang, Lu Zhong, Kaiyou Qian
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Patent number: 8852999Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.Type: GrantFiled: September 19, 2011Date of Patent: October 7, 2014Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath