Patents by Inventor Shrinivas KUDEKAR

Shrinivas KUDEKAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942964
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Publication number: 20240022752
    Abstract: A system and method for managing encoded information in a real-time screen-to-camera communication environment are disclosed. The system converts information into a pre-defined number of characters and generates data symbols in shapes and pilot symbols corresponding to the characters. Further, the system embeds the data symbols in media content frames and modulates pixels and boundaries for display of display device, based on luminance, and adaptively displays frames as temporal-complementary frames. Furthermore, the system detects frames from recorded content, extracts data symbols based on grid and fixed pattern, and detects bit values by analyzing color differences. Additionally, the system generates information based on the detected bit values and outputs the information on an user device display, including products, recommendations, services, and relevant information related to the media content.
    Type: Application
    Filed: May 23, 2023
    Publication date: January 18, 2024
    Inventor: Shrinivas Kudekar
  • Patent number: 11855776
    Abstract: Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size and allocation of the information bits is based on a base sequence of a given length. During decoding, a decoder assigns different bit types to channels instances by dividing a codeword into a plurality of groups and assigning bit types to channel instances of the plurality of groups using the base sequence.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Shrinivas Kudekar, Joseph Binamira Soriaga, Hari Sankar, Changlong Xu, Chao Wei
  • Patent number: 11831332
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARD) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Publication number: 20230327683
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Application
    Filed: June 1, 2023
    Publication date: October 12, 2023
    Inventors: Shrinivas KUDEKAR, Thomas Joseph RICHARDSON
  • Publication number: 20230275599
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARD) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Application
    Filed: November 1, 2022
    Publication date: August 31, 2023
    Inventors: Thomas Joseph RICHARDSON, Shrinivas KUDEKAR
  • Patent number: 11671120
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: June 6, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Se Yong Park, Alexandros Manolakos, Krishna Kiran Mukkavilli, Vincent Loncke, Joseph Binamira Soriaga, Jing Jiang, Thomas Joseph Richardson
  • Patent number: 11496154
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Publication number: 20220224356
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Application
    Filed: January 28, 2022
    Publication date: July 14, 2022
    Inventors: Shrinivas KUDEKAR, Thomas Joseph Richardson
  • Publication number: 20220190958
    Abstract: Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size and allocation of the information bits is based on a base sequence of a given length. During decoding, a decoder assigns different bit types to channels instances by dividing a codeword into a plurality of groups and assigning bit types to channel instances of the plurality of groups using the base sequence.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 16, 2022
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Shrinivas Kudekar, Joseph Binamira Soriaga, Hari Sankar, Changlong Xu, Chao Wei
  • Patent number: 11277151
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 15, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Publication number: 20220069841
    Abstract: Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Changlong Xu, Shrinivas Kudekar, Thomas Joseph Richardson, Joseph Binamira Soriaga
  • Patent number: 11239860
    Abstract: Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 1, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 11239947
    Abstract: Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size and allocation of the information bits is based on a base sequence of a given length. During decoding, a decoder assigns different bit types to channels instances by dividing a codeword into a plurality of groups and assigning bit types to channel instances of the plurality of groups using the base sequence.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 1, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Shrinivas Kudekar, Joseph Binamira Soriaga, Hari Sankar, Changlong Xu, Chao Wei
  • Patent number: 11211946
    Abstract: Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Shrinivas Kudekar, Thomas Richardson, Joseph Binamira Soriaga
  • Patent number: 11206626
    Abstract: An apparatus are provided for wireless communication at a base station with improved PBCH construction and decoding. The base station apparatus constructs a PBCH payload, wherein a bit location is selected for encoding a plurality of bits of the PBCH based on an estimated reliability for the corresponding bits location wherein the plurality of bits comprises frozen bits, unknown bits that are unknown to a user equipment, and potentially known bits that are potentially known by the user equipment. The apparatus transmits the PBCH payload in at least one of a plurality of SS blocks. A UE receiving the PBCH decodes the PBCH based on a successive decoding order. The successive decoding order may be based on an estimated reliability for the corresponding bits, e.g., in which potentially known bits are decoded prior to unknown bits.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 21, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Bilal Sadiq, Juergen Cezanne, Shrinivas Kudekar, Navid Abedini, Muhammad Nazmul Islam
  • Patent number: 11043966
    Abstract: Techniques and apparatus are provided for efficiently generating multiple lifted low-density parity-check (LDPC) codes for a range of block lengths and having good performance. A method for wireless communications by a transmitting device generally includes selecting integer lifting values for a first lifting size value Z, selected from a range of lifting size values, wherein the selected integer lifting value is greater than a maximum lifting size value of the range of lifting size values; determining one or more integer lifting values for generating at least a second lifted LDPC code having a second lifting size value based on an operation involving the second lifting size value and the selected one or more integer lifting values for generating the first lifted LDPC code; encoding a set of information bits based on the second lifted LDPC to produce a code word; and transmitting the code word.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: June 22, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Patent number: 11032026
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 8, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Patent number: 11031953
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 8, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar
  • Publication number: 20210167891
    Abstract: Methods, systems, and devices for encoding and decoding are described. To encode a vector, an encoder allocates information bits of the vector to channel instances of a channel that are separated into groups. The groups may vary in size and allocation of the information bits is based on a base sequence of a given length. During decoding, a decoder assigns different bit types to channels instances by dividing a codeword into a plurality of groups and assigning bit types to channel instances of the plurality of groups using the base sequence.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 3, 2021
    Inventors: Jing Jiang, Gabi Sarkis, Yang Yang, Shrinivas Kudekar, Joseph Soriaga, Hari Sankar, Changlong Xu, Chao Wei