Patents by Inventor Shriram Shivaraman

Shriram Shivaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098887
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Jack T. KAVALIEROS, Sean MA, Seung Hoon SUNG, Nazila HARATIPOUR, Tahir GHANI, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Publication number: 20200098934
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, where the channel layer includes a first region and a second region, and the first region has a first dopant concentration. A gate electrode is above the first region of the channel layer and separated from the channel layer by a gate dielectric layer. A spacer is next to the gate electrode to separate the gate electrode from a drain electrode or a source electrode above the channel layer. The spacer includes a dopant material in contact with the second region of the channel layer, and the second region has a second dopant concentration different from the first dopant concentration in the first region. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Shriram SHIVARAMAN, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Seung Hoon SUNG, Nazila HARATIPOUR, Abhishek SHARMA
  • Publication number: 20200098931
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Abhishek SHARMA, Nazila HARATIPOUR, Seung Hoon SUNG, Benjamin CHU-KUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Matthew V. METZ, Arnab SEN GUPTA
  • Publication number: 20200098930
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
  • Publication number: 20200066912
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Rafael RIOS, Shriram SHIVARAMAN, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC
  • Publication number: 20200035839
    Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200027883
    Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
  • Publication number: 20200013861
    Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.
    Type: Application
    Filed: March 31, 2017
    Publication date: January 9, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Shriram Shivaraman, Tahir Ghani, Jack T. Kavalieros, Cory E. Weber
  • Publication number: 20200006570
    Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200006572
    Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Abhishek A. SHARMA, Yih WANG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Benjamin CHU-KUNG, Seung Hoon SUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Matthew V. METZ
  • Publication number: 20200006575
    Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Gilbert DEWEY, Aaron LILAK, Van H. LE, Abhishek A. SHARMA, Tahir GHANI, Willy RACHMADY, Rishabh MEHANDRU, Nazila HARATIPOUR, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Seung Hoon SUNG, Shriram SHIVARAMAN
  • Publication number: 20190393223
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Application
    Filed: March 31, 2017
    Publication date: December 26, 2019
    Inventors: Abhishek Anil SHARMA, Van H. LE, Gilbert William DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Yih WANG, Shriram SHIVARAMAN
  • Publication number: 20190393356
    Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Van H. LE, Seung Hoon SUNG, Benjamin CHU-KUNG, Miriam RESHOTKO, Matthew METZ, Yih WANG, Gilbert DEWEY, Jack KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Abhishek SHARMA, Shriram SHIVARAMAN
  • Publication number: 20190385949
    Abstract: Integrated circuit structures are described that include back end memory devices that are integrated into one or more back end interconnect layers of an integrated circuit. Examples of the back end memory devices described include one transistor and one capacitor (ā€œ1T/1Cā€) memory cell devices that use an oxide semiconductor layer (e.g., indium gallium zinc oxide) as an element of the transistor portion (1T) of the back end memory cell. This produces a memory device with a low off state leakage current, improving memory device performance while also reducing memory device size.
    Type: Application
    Filed: December 27, 2016
    Publication date: December 19, 2019
    Applicant: INTEL CORPORATION
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Yih Wang, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20190378932
    Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Van H. LE, Inanc MERIC, Gilbert DEWEY, Sean MA, Abhishek A. SHARMA, Miriam RESHOTKO, Shriram SHIVARAMAN, Kent MILLARD, Matthew V. METZ, Wilhelm MELITZ, Benjamin CHU-KUNG, Jack KAVALIEROS
  • Publication number: 20190363193
    Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.
    Type: Application
    Filed: December 28, 2016
    Publication date: November 28, 2019
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek A. Sharma, Shriram Shivaraman, Van H. Le, Ravi Pillarisetty, Tahir Ghani
  • Publication number: 20190355725
    Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.
    Type: Application
    Filed: December 28, 2016
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: Van Le, Abhishek Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Tahir Ghani, Jack Kavalieros
  • Publication number: 20190304982
    Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Yih WANG, Benjamin CHU-KUNG, Shriram SHIVARAMAN
  • Publication number: 20190305137
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani