Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract: A method of generating a mask for fabrication of a physical layer of an integrated circuit is provided. Multiple design layers are provided which comprise a programmable subcomponent configuration layer defining logical configurations of programmable subcomponents. A mask generation procedure transforms a selected design layer into a mask for fabrication of a physical layer. A mask modification procedure amends the mask to ensure that the physical layer will be reliably fabricated when using the mask. A non-functional design layer which does not represent one of said multiple physical layers represents further possible positions for said set of physical structures in said selected physical layer, which are not represented in said programmable subcomponent configuration layer. The mask modification procedure treats the non-functional design layer as a programmable subcomponent configuration layer.