Patents by Inventor Shrivathsa BHARGAVRAVICHANDRAN

Shrivathsa BHARGAVRAVICHANDRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9298868
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 29, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vikas Agrawal, Shrivathsa Bhargavravichandran, Binh Pham, Jay Chen, Sridhar Krishnamurthy, Umang Shah, Chi Keung Lee
  • Publication number: 20150199464
    Abstract: A method of designing a floorplan for an integrated circuit comprises executing one or more automated placement processes on one or more seed floorplans to generate at least one output floorplan for each of the one or more seed floorplans, wherein the one or more automated placement processes are included in a plurality of pre-selected automated placement processes. The method further comprises computing a quality score for each output floorplan and, based on the quality scores, selecting at least one of the output floorplans for further execution via at least one automated placement process included in the plurality of pre-selected automated placement processes.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Patrick Alan SPROULE, Shrivathsa BHARGAVRAVICHANDRAN, Karthik SUNDARAM, Kevin SAVIDGE
  • Publication number: 20140380257
    Abstract: A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Inventors: Vikas AGRAWAL, Shrivathsa BHARGAVRAVICHANDRAN, Binh PHAM, Jay CHEN, Sridhar KRISHNAMURTHY, Umang SHAH, Chi Keung LEE