Patents by Inventor Shruti Vivek Thombare

Shruti Vivek Thombare has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220389579
    Abstract: Provided herein are methods and apparatus for deposition of pure metal films. The methods involve the use of oxygen-containing precursors. The metals include molybdenum (Mo) and tungsten (W). To deposit pure films with no more than one atomic percentage oxygen, the reducing agent to metal precursor ratio is significantly greater than 1. Molar ratios of 100:1 to 10000:1 may be used in some embodiments.
    Type: Application
    Filed: July 21, 2022
    Publication date: December 8, 2022
    Inventors: Shruti Vivek THOMBARE, Gorun BUTAIL, Patrick A. VAN CLEEMPUT, Ilanit FISHER
  • Publication number: 20220375792
    Abstract: Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.
    Type: Application
    Filed: October 14, 2020
    Publication date: November 24, 2022
    Inventors: Lawrence SCHLOSS, Shruti Vivek THOMBARE, Zhongbo YAN, Patrick A. VAN CLEEMPUT, Joshua COLLINS
  • Publication number: 20220359211
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Patrick A. VAN CLEEMPUT, Shruti Vivek THOMBARE, Michal DANEK
  • Publication number: 20220290300
    Abstract: Various showerheads and methods are provided. A showerhead may include a faceplate partially defined by a front surface and a back surface, a back plate having a gas inlet, a first conical frustum surface, and a second conical frustum surface, a plenum volume fluidically connected to the gas inlet and at least partially defined by the gas inlet, the back surface of the faceplate, the first conical frustum surface, and the second conical frustum surface, and a baffle plate positioned within the plenum volume, and having a plurality of baffle plate through-holes extending through the baffle plate. The second conical frustum surface may be positioned radially outwards from the first conical frustum surface with respect to a center axis of the showerhead, and the second conical frustum surface may be positioned along the center axis farther from the gas inlet than the first conical frustum surface.
    Type: Application
    Filed: August 19, 2020
    Publication date: September 15, 2022
    Inventors: Ravi Vellanki, Eric H. Lenz, Vinayakaraddy Gulabal, Sanjay Gopinath, Michal Danek, Prodyut Majumder, Novy Tjokro, Yen-Chang Chen, Shruti Vivek Thombare, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20220223471
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: July 14, 2022
    Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
  • Publication number: 20220013365
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication, The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.
    Type: Application
    Filed: November 18, 2019
    Publication date: January 13, 2022
    Applicant: Lam Research Corporation
    Inventors: Patrick A. van Cleemput, Shruti Vivek Thombare, Michal Danek
  • Publication number: 20210140043
    Abstract: Provided herein are methods and apparatus for deposition of pure metal films. The methods involve the use of oxygen-containing precursors. The metals include molybdenum (Mo) and tungsten (W). To deposit pure films with no more than one atomic percentage oxygen, the reducing agent to metal precursor ratio is significantly greater than 1. Molar ratios of 100:1 to 10000:1 may be used in some embodiments.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 13, 2021
    Inventors: Shruti Vivek Thombare, Gorun Butail, Patrick A. van Cleemput, Ilanit Fisher
  • Publication number: 20200402846
    Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.
    Type: Application
    Filed: November 19, 2018
    Publication date: December 24, 2020
    Applicant: Lam Research Corporation
    Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick van Cleemput, Gorun Butail
  • Publication number: 20200365456
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 19, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
  • Patent number: 10777453
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20200075403
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10510590
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20180294187
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 11, 2018
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 9478411
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Patent number: 9478438
    Abstract: Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Michal Danek
  • Publication number: 20160056037
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Publication number: 20160056053
    Abstract: Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Michal Danek