Patents by Inventor Shu-Feng Wu
Shu-Feng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071538Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
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Patent number: 10783818Abstract: A dual gate transistor circuit, a pixel circuit, and a gate drive circuit are provided. The dual gate transistor circuit includes a dual gate transistor, a first diode, and a second diode. The dual gate transistor has a first gate and a second gate, and the first gate receives a drive signal. The first diode is connected in series between the first gate and the second gate according to a first-polarity direction. The second diode is connected in series between the first gate and the second gate according to a second-polarity direction. The first-polarity direction is opposite to the second-polarity direction.Type: GrantFiled: June 13, 2019Date of Patent: September 22, 2020Assignee: Au Optronics CorporationInventors: Shu-Wei Tsao, Chi-Jui Lin, Shu-Feng Wu, Wei-Sheng Yu
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Publication number: 20200035139Abstract: A dual gate transistor circuit, a pixel circuit, and a gate drive circuit are provided. The dual gate transistor circuit includes a dual gate transistor, a first diode, and a second diode. The dual gate transistor has a first gate and a second gate, and the first gate receives a drive signal. The first diode is connected in series between the first gate and the second gate according to a first-polarity direction. The second diode is connected in series between the first gate and the second gate according to a second-polarity direction. The first-polarity direction is opposite to the second-polarity direction.Type: ApplicationFiled: June 13, 2019Publication date: January 30, 2020Applicant: Au Optronics CorporationInventors: Shu-Wei Tsao, Chi-Jui Lin, Shu-Feng Wu, Wei-Sheng Yu
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Patent number: 8987739Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.Type: GrantFiled: March 20, 2012Date of Patent: March 24, 2015Assignee: Au Optronics CorporationInventors: Chen-Yuan Tu, Yih-Chyun Kao, Shu-Feng Wu, Chun-Nan Lin
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Patent number: 8760593Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.Type: GrantFiled: August 5, 2008Date of Patent: June 24, 2014Assignee: Au Optronics CorporationInventors: Po-Lin Chen, Kuo-Yuan Tu, Wen-Ching Tsai, Chun-Nan Lin, Shu-Feng Wu
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Publication number: 20130168682Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.Type: ApplicationFiled: March 20, 2012Publication date: July 4, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chen-Yuan Tu, Yih-Chyun Kao, Shu-Feng Wu, Chun-Nan Lin
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Publication number: 20120261755Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a passivation layer, and a pixel electrode is provided. The TFT includes a gate, a dielectric layer, a channel layer, and a source/drain sequentially disposed on the substrate. The source/drain is disposed on a portion of the channel layer and has a semiconductor layer, a barrier layer and a metal layer. The barrier layer is disposed on a portion of the semiconductor layer. The metal layer is disposed on the barrier layer. The barrier layer is in contact with the semiconductor layer and the metal layer. Both of the metal layer and the barrier layer are positioned within a projection area of the semiconductor layer. The passivation layer covers the TFT and the dielectric layer and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.Type: ApplicationFiled: May 22, 2012Publication date: October 18, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Po-Lin Chen, Chun-Nan Lin, Shu-Feng Wu, Wen-Ching Tsai
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Patent number: 8212256Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.Type: GrantFiled: April 2, 2008Date of Patent: July 3, 2012Assignee: Au Optronics CorporationInventors: Po-Lin Chen, Chun-Nan Lin, Shu-Feng Wu, Wen-Ching Tsai
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Patent number: 8062917Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.Type: GrantFiled: August 13, 2010Date of Patent: November 22, 2011Assignee: AU Optronics CorporationInventors: Chun-Nan Lin, Kuo-Yuan Tu, Shu-Feng Wu, Wen-Ching Tsai
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Patent number: 7922921Abstract: The present invention includes the steps of providing a substrate having a main surface; depositing a dual-metal layer such as Mo/AlNd, MoW/AlNd, MoW/Al onto the main surface of the substrate; defining gate and word line patter using a layer of photoresist; and using the photoresist as an etching mask, a first metal dry etching process is carried out to etch the dual-metal layer at an etching selectivity that is significantly higher than prior art. The first metal dry etching process uses oxygen/fluorine containing etching gas mixture and oxygen/chlorine containing etching gas mixture to form the dual-metal gate and word line pattern having slightly oblique sidewalls. End point detection mode detected at 704 nm is used in the first metal dry etching process.Type: GrantFiled: March 17, 2004Date of Patent: April 12, 2011Assignee: AU Optronics Corp.Inventors: Chih-Chung Chuang, Shin-Jien Kuo, Chao-Yun Cheng, Shu-Feng Wu
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Patent number: 7902670Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.Type: GrantFiled: April 23, 2007Date of Patent: March 8, 2011Assignee: AU Optronics CorporationInventors: Chun-Nan Lin, Kuo-Yuan Tu, Shu-Feng Wu, Wen-Ching Tsai
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Publication number: 20110014788Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.Type: ApplicationFiled: August 13, 2010Publication date: January 20, 2011Applicant: AU OPTRONICS CORPORATIONInventors: Chun-Nan Lin, Kuo-Yuan Tu, Shu-Feng Wu, Wen-Ching Tsai
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Publication number: 20090153056Abstract: A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.Type: ApplicationFiled: April 2, 2008Publication date: June 18, 2009Applicant: AU OPTRONICS CORPORATIONInventors: Po-Lin Chen, Chun-Nan Lin, Shu-Feng Wu, Wen-Ching Tsai
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Publication number: 20090101903Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.Type: ApplicationFiled: August 5, 2008Publication date: April 23, 2009Inventors: Po-Lin Chen, Kuo-Yuan Tu, Wen-Ching Tsai, Chun-Nan Lin, Shu-Feng Wu
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Publication number: 20080009108Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.Type: ApplicationFiled: April 23, 2007Publication date: January 10, 2008Applicant: AU OPTRONICS CORPORATIONInventors: Chun-Nan Lin, Kuo-Yuan Tu, Shu-Feng Wu, Wen-Ching Tsai
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Patent number: 6926014Abstract: A method for cleaning a plasma chamber after metal etching. First, a substrate having a metal layer thereon is placed in a plasma chamber. Next, the metal layer is etched. Finally, the substrate is removed from the plasma chamber to perform a dry cleaning which includes the following steps. First, the inner wall of the plasma chamber is cleaned by plasma etching using oxygen as a process gas. Next, the top and bottom electrode plates in the plasma chamber are cleaned by plasma etching using chlorine and boron chloride as process gases. Next, the inner wall of the plasma chamber is cleaned again by plasma etching using sulfur hexafluoride and oxygen as process gases. Finally, oxygen and helium used as purging gases are injected into the plasma chamber and exhausted from therein.Type: GrantFiled: May 22, 2003Date of Patent: August 9, 2005Assignee: Au Optronics Corp.Inventors: Chao-Yun Cheng, Shin-Jien Kuo, Chih-Chung Chuang, Shu-Feng Wu
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Publication number: 20040209471Abstract: The present invention includes the steps of providing a substrate having a main surface; depositing a dual-metal layer such as Mo/AlNd, MoW/AlNd, MoW/Al onto the main surface of the substrate; defining gate and word line patter using a layer of photoresist; and using the photoresist as an etching mask, a first metal dry etching process is carried out to etch the dual-metal layer at an etching selectivity that is significantly higher than prior art. The first metal dry etching process uses oxygen/fluorine containing etching gas mixture and oxygen/chlorine containing etching gas mixture to form the dual-metal gate and word line pattern having slightly oblique sidewalls. End point detection mode detected at 704 nm is used in the first metal dry etching process.Type: ApplicationFiled: March 17, 2004Publication date: October 21, 2004Inventors: Chih-Chung Chuang, Shin-Jien Kuo, Chao-Yun Cheng, Shu-Feng Wu
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Publication number: 20040103914Abstract: A method for cleaning a plasma chamber after metal etching. First, a substrate having a metal layer thereon is placed in a plasma chamber. Next, the metal layer is etched. Finally, the substrate is removed from the plasma chamber to perform a dry cleaning which includes the following steps. First, the inner wall of the plasma chamber is cleaned by plasma etching using oxygen as a process gas. Next, the top and bottom electrode plates in the plasma chamber are cleaned by plasma etching using chlorine and boron chloride as process gases. Next, the inner wall of the plasma chamber is cleaned again by plasma etching using sulfur hexafluoride and oxygen as process gases. Finally, oxygen and helium used as purging gases are injected into the plasma chamber and exhausted from therein.Type: ApplicationFiled: May 22, 2003Publication date: June 3, 2004Applicant: AU Optronics Corp.Inventors: Chao-Yun Cheng, Shin-Jien Kuo, Chih-Chung Chuang, Shu-Feng Wu