Patents by Inventor Shu Huang

Shu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226033
    Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
  • Publication number: 20210160758
    Abstract: A network path selection method and a network node device using the same are disclosed. The network path selection method includes: determining whether a first uplink time parameter table is received from the first relay node device and whether a second uplink time parameter table is received from the second relay node device; when the first uplink time parameter table is received from the first relay node device and the second uplink time parameter table is received from the second relay node device, calculating a first estimated uplink time parameter according to the first uplink time parameter table and a second estimated uplink time parameter according to the second uplink time parameter table; and determining to connect to a gateway via one of the first relay node device and the second relay node device according to the first estimated uplink time parameter and the second estimated uplink time parameter.
    Type: Application
    Filed: July 23, 2020
    Publication date: May 27, 2021
    Inventors: Kuo-Shu HUANG, Wen-Chieh WANG, Wei-Ru TSENG, Wei-Yang TENG
  • Publication number: 20210153039
    Abstract: A network device including a main bridge, a first bridge, a controller, and an Ethernet port is provided. When the Ethernet port is connected to a mesh network, the processing unit performs the following steps: controlling the Ethernet port to transmit a first broadcast packet; when the Ethernet port receives a second broadcast packet, parsing the second broadcast packet to extract the packet path information to determine whether a path loop exists; determining, according to the Ethernet interface weight (EIW), the slave interface uplink weight (SIUW), and the master device weight (MW) carried by the first broadcast packet and the second broadcast packet, (1) whether the network device plays a master device role, (2) whether the bridge of the Ethernet port is set as the main bridge or the first bridge, and (3) whether the Ethernet port allows data transmission.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 20, 2021
    Inventors: Kuo-Shu HUANG, Tsung-Hsien HSIEH, Chih-Fang LEE
  • Publication number: 20210143556
    Abstract: An antenna array is provided, which may include a connection portion and a plurality of antenna units. The antenna units may be disposed on the two sides of the connection portion respectively. The proximal end of each of the antenna units may be connected to the connection portion and the distal end of one or more of the antenna units may be grounded. The length of each of the antenna units may be less than or equal to ¼ wavelength of the operating frequency of the antenna array, and the distance between any two adjacent antenna units may be less than or equal to ½ wavelength of the operating frequency of the antenna array.
    Type: Application
    Filed: February 20, 2020
    Publication date: May 13, 2021
    Inventors: CHUN-CHI LIN, CHANG-SHENG CHEN, GUO-SHU HUANG
  • Publication number: 20210129356
    Abstract: A robot arm including a first joint, a second joint, and a coupling element is provided. The first joint has a first inclined surface. The second joint is jointed to the first joint and has a second inclined surface. The coupling element has a third inclined surface and a fourth inclined surface opposite to the third inclined surface, wherein the third inclined surface contacts the first inclined surface, and the fourth inclined surface contacts the second inclined surface.
    Type: Application
    Filed: August 10, 2020
    Publication date: May 6, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ping LEE, Hen-Diong KNG, Hao-Yan WU, Tsang-Fang JENG, Shu HUANG, Hung-Hsiu YU
  • Publication number: 20210083086
    Abstract: The present invention relates to an epitaxial structure of N-face group III nitride, its active device, and its gate protection device. The epitaxial structure of N-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlyGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Inventor: CHIH-SHU HUANG
  • Publication number: 20210083083
    Abstract: The present invention relates to an epitaxial structure of Ga-face group III nitride, its active device, and its gate protection device. The epitaxial structure of Ga-face AlGaN/GaN comprises a silicon substrate, a buffer layer (C-doped) on the silicon substrate, an i-GaN (C-doped) layer on the buffer layer (C-doped), an i-AlyGaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By connecting a depletion-mode (D-mode) AlGaN/GaN high electron mobility transistor (HEMT) to the gate of a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the gate of the p-GaN gate E-mode AlGaN/GaN HEMT can be protected under any gate voltage.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Inventor: CHIH-SHU HUANG
  • Publication number: 20210058318
    Abstract: A transmission system, a transmission device and a transmission path allocation method are provided. The transmission path allocation method is configured to transmit a plurality of data packets through at least two transmission paths. Each of the transmission paths has a send buffer. The transmission path allocation method includes the following steps. A transmission time length for each of the transmission paths is analyzed according to an output data variation of each of the send buffers. Each of the data packets is allocated to the transmission paths according to each of the transmission time lengths. A sequential code is attached to each of the data packets. Each of the data packets is transmitted.
    Type: Application
    Filed: June 29, 2020
    Publication date: February 25, 2021
    Inventor: Kuo-Shu HUANG
  • Patent number: 10928933
    Abstract: A mouse device includes a casing, a switch, a button, a travel distance adjustment and a knob structure. The button is exposed to a top side of the casing. A first end of the travel distance adjustment assembly is contacted with the button. A second end of the travel distance adjustment assembly includes an internal thread structure. The internal thread structure of the travel distance adjustment assembly is engaged with an external thread structure of the knob structure. While an operating part of the knob structure is rotated, the knob structure is not moved and the travel distance adjustment assembly is moved upwardly relative to the knob structure to push the force-exerted part upwardly. Consequently, a triggering speed of the switch is increased.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 23, 2021
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Chun-Lin Chu, Shu-An Huang
  • Publication number: 20210050314
    Abstract: A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.
    Type: Application
    Filed: November 3, 2020
    Publication date: February 18, 2021
    Inventors: HUNG-SHU HUANG, MING-CHYI LIU
  • Publication number: 20210013317
    Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventor: CHIH-SHU HUANG
  • Patent number: 10886381
    Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 5, 2021
    Inventor: Chih-Shu Huang
  • Publication number: 20200363831
    Abstract: A keyboard device includes a keyboard module and a palm rest module. The palm rest module is arranged beside a lateral side of the keyboard module, and supports a wrist of a user. The palm rest module includes a pedestal, a casing and an adjusting element. The casing is disposed on the pedestal. The adjusting element is arranged between the pedestal and the casing. A position of the casing relative to the pedestal is adjustable through the adjusting element. In a first usage state, the casing is moved toward the keyboard module or moved away from the keyboard module through the adjusting element. In a second usage state, the casing is rotated about the adjusting element and relative to the keyboard module, so that an included angle is formed between the casing and the lateral side of the keyboard module.
    Type: Application
    Filed: September 23, 2019
    Publication date: November 19, 2020
    Inventors: Shu-An Huang, Chun-Lin Chu
  • Patent number: 10840198
    Abstract: A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 10833163
    Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 10, 2020
    Inventor: Chih-Shu Huang
  • Publication number: 20200321348
    Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Inventors: Hung-Shu Huang, Ming Chyi Liu
  • Publication number: 20200298763
    Abstract: A vehicle rearview mirror includes a reflector having a light-transmissive pattern, and a light emitting module disposed behind the reflector and including a reflection base, a light source and a lens. The reflection base is hollow-shaped and provided on the inner wall thereof with a plurality of reflecting surfaces which gradually tilt one after another. The lens is mounted to the reflection base and has an inside surface and an outside surface. The inside surface is a matt surface. The outside surface faces the light-transmissive pattern. The light source is disposed on the reflection base in a way that the light emitted by the light source is reflected to the inside surface by the reflecting surfaces.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 24, 2020
    Inventor: PIN-SHU HUANG
  • Publication number: 20200298760
    Abstract: A vehicle rearview mirror includes a reflector having a light-transmissive pattern, and a light emitting module including a case, a light source and a light guide. The light guide is disposed in the case and has an illuminating surface and a prism surface opposite to the illuminating surface for total reflection. The light guide is provided on a side thereof with an incidence surface. The light source is disposed in the case and faces the incidence surface in a way that the light emitted by the light source enters the light guide through the incidence surface and reflected by the prism surface to the illuminating surface which faces the light-transmissive pattern, thereby showing the light-transmissive pattern.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 24, 2020
    Inventor: PIN-SHU HUANG
  • Publication number: 20200295015
    Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Shu HUANG, Ming-Chyi LIU
  • Publication number: 20200292157
    Abstract: A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 ?m and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Inventors: CHI-CHIH PU, CHEN-HONG LEE, SHIH-YU YEH, WEI-KANG CHENG, SHYI-MING PAN, SIANG-FU HONG, CHIH-SHU HUANG, TZU-HSIANG WANG, SHIH-CHIEH TANG, CHENG-KUANG YANG