Abstract: A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

Abstract: Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.

Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has multiple support structures, and the support structures are positioned at respective corner portions of the substrate. Multiple openings penetrate through the lid to expose a space containing the semiconductor die.

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.