Patents by Inventor Shu-Ting Tsai
Shu-Ting Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160336231Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
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Patent number: 9455158Abstract: A stacked semiconductor device and a method of forming the stacked semiconductor device are provided. A plurality of integrated circuits are bonded to one another to form the stacked semiconductor device. After each bonding step to bond an additional integrated circuit to a stacked semiconductor device formed at the previous bonding step, a plurality of conductive plugs are formed to electrically interconnect the additional integrated circuit to the stacked semiconductor device formed at the previous bonding step.Type: GrantFiled: September 11, 2014Date of Patent: September 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Szu-Ying Chen, Jeng-Shyan Lin, Tzu-Hsuan Hsu, Feng-Chi Hung, Dun-Nian Yaung
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Publication number: 20160276383Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
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Patent number: 9412719Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: December 19, 2013Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, U-Ting Chen, Shih Pei Chou
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Patent number: 9406712Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: GrantFiled: May 29, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
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Publication number: 20160204154Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 9356066Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.Type: GrantFiled: May 21, 2013Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
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Patent number: 9293392Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: September 6, 2013Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Lin Chia-Chieh, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
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Patent number: 9287312Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: GrantFiled: December 30, 2013Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shu-Ting Tsai, Jeng-Shyan Lin, Shuang-Ji Tsai, Wen-I Hsu
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Publication number: 20150348917Abstract: An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.Type: ApplicationFiled: September 19, 2014Publication date: December 3, 2015Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung
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Publication number: 20150348874Abstract: An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.Type: ApplicationFiled: August 25, 2014Publication date: December 3, 2015Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung
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Publication number: 20150348905Abstract: A stacked semiconductor device and a method of forming the stacked semiconductor device are provided. A plurality of integrated circuits are bonded to one another to form the stacked semiconductor device. After each bonding step to bond an additional integrated circuit to a stacked semiconductor device formed at the previous bonding step, a plurality of conductive plugs are formed to electrically interconnect the additional integrated circuit to the stacked semiconductor device formed at the previous bonding step.Type: ApplicationFiled: September 11, 2014Publication date: December 3, 2015Inventors: Shu-Ting Tsai, Szu-Ying Chen, Jeng-Shyan Lin, Tzu-Hsuan Hsu, Feng-Chi Hung, Dun-Nian Yaung
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Publication number: 20150287757Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
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Publication number: 20150279893Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: ApplicationFiled: June 15, 2015Publication date: October 1, 2015Inventors: Min-Feng KAO, Dun-Nian YAUNG, Jen-Cheng LIU, Chun-Chieh CHUANG, Feng-Chi HUNG, Shuang-Ji TSAI, Jeng-Shyan LIN, Shu-Ting TSAI, Wen-I HSU
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Publication number: 20150279891Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: U-Ting Chen, Shu-Ting Tsai, Cheng-Ying Ho, Tzu-Hsuan Hsu, Shih Pei Chou
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Patent number: 9147702Abstract: One or more embodiments of techniques or systems for mitigating dark current of an image sensor are provided herein. Generally, a silicon interface, such as an edge of a dielectric region or an edge between a back side interface (BSI) region and a pass region, is a source of electrons or holes which cause dark current. In some embodiments, the image sensor includes a surface protect region. For example, the surface protect region is doped with a first doping type and a photo-diode of the image sensor is doped with the same first doping type. In this manner, the surface protect region acts as an electron magnet or a hole magnet for electrons or holes from the silicon interface, thus mitigating electrons or holes from the silicon interface from being collected by the photo-diode, for example.Type: GrantFiled: February 18, 2013Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Shu-Ting Tsai, Shuang-Ji Tsai
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Publication number: 20150249057Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai
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Patent number: 9076715Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: GrantFiled: November 26, 2013Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
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Publication number: 20150187701Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, U-Ting Chen
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Publication number: 20150179613Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen