Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.

Abstract: Disclosed is an IC voltage determining method including: executing a static timing analysis according to a circuit design to obtain data of a critical path and then generating a netlist; executing a circuit parameter simulation and Monte Carlo simulation with the netlist according to a regular voltage and prescribed parameters to obtain a circuit parameter reference value and a variance of circuit parameter values; executing an adaptive voltage scaling analysis according to a voltage range to obtain a voltage-versus-parameter relation indicative of the number of times that each of circuit parameter deviations that are respectively associated with predetermined voltages within the predetermined voltage range is of the variance; and testing an IC according to the regular voltage to obtain a circuit parameter test value and determining the IC voltage according to the voltage-versus-parameter relation and a difference between the circuit parameter test value and the circuit parameter reference value.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: An IC design data base generating method, including: receiving a condition parameter, which comprises a process parameter and an operating parameter range comprising at least one operating parameter; and testing at least one cell according to the process parameter and the operating parameter range to generate a delay value data base. The delay value data base comprises a plurality of delay values, wherein the plurality of delay values for an identical cell correspond to the operating parameter range with an identical type but different value. An IC design method using the delay value data base is also disclosed.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: A power rail design method is disclosed that includes the steps outlined below. A plurality of power rails and a plurality of power domains corresponding thereto in an integrated circuit design file are identified. A design rule check for a plurality of circuit units in the integrated circuit design file is performed to retrieve a plurality of non-violating circuit regions that correspond to the power rails in each of the power domains. The power rails corresponding to at least part of the plurality of non-violating circuit regions in the integrated circuit design file are widened to occupy at least part of the non-violating circuit regions for the plurality of power rails.

Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.

Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: A planning method for power metal lines is provided. The planning method includes selecting a block to plan, the block including a first metal layer and a second metal layer therebelow. The first metal layer includes a plurality of first metal lines along a first direction and the second metal layer includes a plurality of second metal lines along a second direction. The block includes a length in the first direction and a width in the second direction. According to a ratio of the length and the width of the block, a line width adjustment procedure is performed to adjust a first line width of each of the first metal lines and a second line width of each of the second metal lines, so that routing congestion can be avoided without affecting the IR drop.

Abstract: A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).

Abstract: An IC design data base generating method, including: receiving a condition parameter, which comprises a process parameter and an operating parameter range comprising at least one operating parameter; and testing at least one cell according to the process parameter and the operating parameter range to generate a delay value data base. The delay value data base comprises a plurality of delay values, wherein the plurality of delay values for an identical cell correspond to the operating parameter range with an identical type but different value. An IC design method using the delay value data base is also disclosed.

Abstract: A method of using simulation software to generate circuit layout includes: (A) determining a plurality of blocks on a circuit board, wherein each block includes an operating space and a reserved space; (B) determining a size of the reserved space of each of the blocks according to at least one specific condition; (C) determining whether to adjust the size of the reserved space of the blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of the blocks determined in step (B).