Patents by Inventor Shuang Meng

Shuang Meng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8207576
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: June 26, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
  • Patent number: 8129289
    Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
  • Patent number: 8123968
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: February 28, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Jingyi Bai, Gurtej S Sandhu, Shuang Meng
  • Patent number: 8119535
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: February 21, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
  • Patent number: 8048812
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: November 1, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Publication number: 20110117743
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Application
    Filed: January 21, 2011
    Publication date: May 19, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Jingyi Bai, Gurtej S. Sandhu, Shuang Meng
  • Publication number: 20110108929
    Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NE3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).
    Type: Application
    Filed: January 14, 2011
    Publication date: May 12, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7884022
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Jingyi Bai, Gurtej S Sandhu, Shuang Meng
  • Patent number: 7872291
    Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: January 18, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7838084
    Abstract: The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed onto the substrate to form a first species monolayer within the deposition chamber from a gaseous precursor. The chemisorbed first species is contacted with remote plasma oxygen derived at least in part from at least one of O2 and O3 and with remote plasma nitrogen effective to react with the first species to form a monolayer comprising an oxide of a component of the first species monolayer. The chemisorbing and the contacting with remote plasma oxygen and with remote plasma nitrogen are successively repeated effective to form porous oxide on the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Shuang Meng, Danny Dynka
  • Publication number: 20100213574
    Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.
    Type: Application
    Filed: May 7, 2010
    Publication date: August 26, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jiutao Li, Shuang Meng
  • Publication number: 20100210111
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.
    Type: Application
    Filed: April 28, 2010
    Publication date: August 19, 2010
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 7723767
    Abstract: A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: May 25, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jiutao Li, Shuang Meng
  • Patent number: 7718540
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: May 18, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
  • Publication number: 20100092891
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Application
    Filed: December 11, 2009
    Publication date: April 15, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 7651951
    Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: January 26, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Publication number: 20080251828
    Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.
    Type: Application
    Filed: September 17, 2007
    Publication date: October 16, 2008
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej Singh Sandhu
  • Patent number: 7431966
    Abstract: The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is chemisorbed onto the substrate to form a first species monolayer within the deposition chamber from a gaseous precursor. The chemisorbed first species is contacted with remote plasma oxygen derived at least in part from at least one of O2 and O3 and with remote plasma nitrogen effective to react with the first species to form a monolayer comprising an oxide of a component of the first species monolayer. The chemisorbing and the contacting with remote plasma oxygen and with remote plasma nitrogen are successively repeated effective to form porous oxide on the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Shuang Meng, Danny Dynka
  • Patent number: 7410898
    Abstract: In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening at a temperature of less than or equal to about 200° C. The deposition can comprise one or both of atomic layer deposition and chemical vapor deposition, and the first material can comprise a metal nitride. A solder-wetting material is formed over a surface of the first material. The solder-wetting material can comprise, for example, nickel. Subsequently, solder is provided within the opening and over the solder-wetting material.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Shuang Meng, Garo J. Derderian
  • Publication number: 20080149593
    Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.
    Type: Application
    Filed: March 4, 2008
    Publication date: June 26, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Jingyi Bai, Gurtej S. Sandhu, Shuang Meng