Abstract: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.

Abstract: Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: Described herein are systems and methods for prime and probe attack mitigation. For example, some methods include, responsive to a cache miss caused by a process, checking whether a priority level of the process satisfies a first priority requirement of a first cache block of a cache with multiple ways including cache blocks associated with respective priority requirements; responsive to the priority level satisfying the first priority requirement, loading the first cache block; and, responsive to the priority level satisfying the first priority requirement, updating the first priority requirement to be equal to the priority level of the process.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: Described herein are systems and methods using noisy instructions for side-channel attack mitigation. For example, some methods include fetching an instruction from a memory into a processor pipeline of a processor core that is configured to execute instructions using an architectural state of the processor core; generating a random number; fissioning the instruction into a set of micro-operations that includes one or more micro-operations that perform the instruction and the random number of noisy micro-operations, wherein each of the noisy micro-operations does not affect the architectural state; executing the set of micro-operations using one or more execution units of the processor pipeline; and, retiring, responsive to completion of execution of the set of micro-operations, the instruction.

Abstract: Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

Abstract: Managing a cache includes parsing a physical address of a data block to determine a partition identifier (ID) and a tag; the partition ID compared against a partition table storing partition IDs. The partition table indicates at least one way partition and at least one set partition corresponding to the partition ID. Based on the partition table, a way partition is determined at which to store the data block, corresponding to a subset of columns of a cache and, based on the partition table and the tag, a set partition is determined at which to store the data block, corresponding to a subset of rows of the cache. A cache address is generated for the data block within a first region of the cache corresponding to an intersection of the way partition and the set partition. The data block is stored to the cache according to the cache address.

Abstract: A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system.

Abstract: Described is a computing system for vector prefetching which includes a hierarchical memory including multiple caches, a missing address storage unit (MASU) associated with each cache which stores prefetch requests suffering a cache miss, a prefetcher which sends prefetch requests towards the hierarchical memory, and a vector prefetch unit. The vector prefetch unit determines existence of at least one of a relationship between a cache block associated with the prefetch request and cache blocks associated with one or more entries in a MASU, or a relationship between cache blocks associated with different entries in a MASU, and sends a vector prefetch request based on related prefetch requests including indicators indicating a starting cache block and a number of related cache blocks to a higher memory level to obtain data associated with each cache block. The hierarchical memory stores the data received in at least one response message from the higher memory level if available.

Abstract: Described herein are systems and methods for prime and probe attack mitigation. For example, some methods include, responsive to a cache miss caused by a process, checking whether a priority level of the process satisfies a first priority requirement of a first cache block of a cache with multiple ways including cache blocks associated with respective priority requirements; responsive to the priority level satisfying the first priority requirement, loading the first cache block; and, responsive to the priority level satisfying the first priority requirement, updating the first priority requirement to be equal to the priority level of the process.

Abstract: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.

Abstract: Memory prefetching in a processor comprises: identifying, in response to memory access instructions, a pattern of addresses; in response to a first memory access request corresponding to a sub-pattern of the pattern of addresses, prefetching a first address that is offset from the sub-pattern of addresses by a first lookahead value, wherein the first address is part of the pattern; measuring a memory access latency; determining, based on the memory access latency, a second lookahead value, wherein the second lookahead value is different from the first lookahead value; and in response to a second memory access request corresponding to the sub-pattern of the pattern of addresses, prefetching a second address, wherein the second address is part of the pattern, and wherein the second address is offset from the sub-pattern of addresses by the second lookahead value.

Abstract: An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.

Abstract: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.

Abstract: Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.

Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.

Abstract: Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.

Abstract: Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.

Abstract: Described herein are systems and methods for microarchitectural sensitive tag flow. For example, some methods include detecting dependence of data stored in a second data storage circuitry on the first instruction, where the first instruction will output a value to be stored in the second data storage circuitry, and wherein the second data storage circuitry is associated with a third tag indicating whether the second data storage circuitry has been designated as storing sensitive data; responsive to the dependence of data stored in the second data storage circuitry on the first instruction, checking whether the second tag indicates a sensitive instruction; and, responsive to the second tag indicating a sensitive instruction, updating the third tag to indicate that data stored in the second data storage circuitry has been designated as sensitive.