Patents by Inventor Shubhendu Sekhar Mukherjee

Shubhendu Sekhar Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11327759
    Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 10, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: David Albert Carlson, Shubhendu Sekhar Mukherjee, Michael Bertone, David Asher, Daniel Dever, Bradley D. Dobbie, Thomas Hummel
  • Patent number: 11307857
    Abstract: Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 19, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Shubhendu Sekhar Mukherjee
  • Patent number: 11263043
    Abstract: Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 1, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Shubhendu Sekhar Mukherjee
  • Patent number: 11263015
    Abstract: Described herein are systems and methods for microarchitectural sensitive tag flow. For example, some methods include detecting dependence of data stored in a second data storage circuitry on the first instruction, where the first instruction will output a value to be stored in the second data storage circuitry, and wherein the second data storage circuitry is associated with a third tag indicating whether the second data storage circuitry has been designated as storing sensitive data; responsive to the dependence of data stored in the second data storage circuitry on the first instruction, checking whether the second tag indicates a sensitive instruction; and, responsive to the second tag indicating a sensitive instruction, updating the third tag to indicate that data stored in the second data storage circuitry has been designated as sensitive.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 1, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Shubhendu Sekhar Mukherjee
  • Patent number: 11194584
    Abstract: Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 7, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Shubhendu Sekhar Mukherjee
  • Patent number: 11176055
    Abstract: A pipeline in a processor core includes: at least one stage that decodes instructions including load instructions that retrieve data stored at respective virtual addresses, at least one stage that issues at least some decoded load instructions out-of-order, and at least one stage that initiates at least one prefetch operation. Copies of page table entries mapping virtual addresses to physical addresses are stored in a TLB. Managing misses in the TLB includes: handling a load instruction issued out-of-order using a hardware page table walker, after a miss in the TLB, handling a prefetch operation using the hardware page table walker, after a miss in the TLB, and handling any software-calling faults triggered by out-of-order load instructions handled by the hardware page table walker differently from any software-calling faults triggered by prefetch operations handled by the hardware page table walker.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Patent number: 11126556
    Abstract: Memory prefetching in a processor comprises: identifying, in response to memory access instructions, a pattern of addresses; and determining, based on the pattern of addresses, an address to prefetch. Determining the address to prefetch comprises: determining, using the pattern of addresses, an index into a history table; retrieving, from the history table and using the index, an offset value, wherein the offset value is not the address to prefetch; and determining the address to prefetch using the offset value and at least one address of the pattern of addresses. The method further comprises prefetching the address to prefetch.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 21, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Shubhendu Sekhar Mukherjee
  • Publication number: 20210173657
    Abstract: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.
    Type: Application
    Filed: October 27, 2020
    Publication date: June 10, 2021
    Inventor: Shubhendu Sekhar Mukherjee
  • Publication number: 20210173651
    Abstract: Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.
    Type: Application
    Filed: October 27, 2020
    Publication date: June 10, 2021
    Inventor: Shubhendu Sekhar Mukherjee
  • Publication number: 20210016728
    Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 21, 2021
    Inventors: Shubhendu Sekhar Mukherjee, William Chu
  • Publication number: 20210011729
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Publication number: 20200379772
    Abstract: A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
  • Patent number: 10846239
    Abstract: A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 24, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Michael Bertone
  • Patent number: 10817300
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 27, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
  • Patent number: 10782896
    Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 22, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
  • Patent number: 10747541
    Abstract: Instructions are executed in a pipeline. Storage accessible to the pipeline stores branch prediction information characterizing results of branch instructions previously executed. A predicted branch result is provided, for at least some branch instructions, based on a selected predictor of multiple predictors. An actual branch result is provided based on an executed branch instruction, and the branch prediction information is updated based on the actual branch result. The predictors include: a first predictor that determines the predicted branch result based on at least a portion of the branch prediction information; and a second predictor that determines the predicted branch result independently from the branch prediction information.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, David Kravitz, Edward J. McLellan
  • Patent number: 10747543
    Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
  • Publication number: 20200210195
    Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
  • Publication number: 20200174945
    Abstract: A first cache module, comprising fully associative cache circuitry, provides TLB entries for a first group of multiple page sizes. A second cache module, comprising set associative cache circuitry, provides TLB entries for a second group of multiple page sizes. Managing TLB entries includes: performing a search in the first cache module based on selected tag bits of a target virtual address that are selected for each TLB entry in the first cache module based on information stored in the first cache module corresponding to one of the multiple pages sizes in the first group, and performing multiple search iterations in the second cache module based on selected index bits and selected tag bits of the target virtual address, where quantities of bits in the selected index bits and the selected tag bits are different for each of the search iterations.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Michael Bertone
  • Publication number: 20200133680
    Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone