Patents by Inventor Shufan Chan

Shufan Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267981
    Abstract: Embodiments of a constant-on-time pulse generator circuit for a DC-DC converter, a pulse width calibration circuit for a DC-DC converter, and a method for operating a constant-on-time pulse generator circuit for a DC-DC converter are disclosed. In an embodiment, a constant-on-time pulse generator circuit for a DC-DC converter includes serially connected digital buffers and a latch circuit having a set terminal, a reset terminal, and an output terminal. The set terminal and the reset terminal are coupled to the serially connected digital buffers. The latch circuit is configured to output a pulse signal with a constant pulse width through the output terminal.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 29, 2019
    Applicant: NXP B.V.
    Inventor: Shufan Chan
  • Patent number: 10340689
    Abstract: One example discloses a power management device, including: a first port configured to be coupled to a first power source; a second port configured to be coupled to a second power source; a switched capacitor converter; and an inductor coupled in parallel with a switch; wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch; and wherein another end of the inductor coupled in parallel with the switch, is coupled between the switched capacitor converter and the second port.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 2, 2019
    Assignee: NXP B.V.
    Inventors: Shufan Chan, Nicholas Seroff, Kisun Lee, Chae Kun Lee
  • Patent number: 10218274
    Abstract: Embodiments of a circuit and method for generating a ripple voltage for a ripple based constant-on-time DC-DC converter are disclosed. A circuit includes a ripple voltage output, a first charging circuit connected to the ripple voltage output, a second charging circuit connected to the ripple voltage output, a charge control circuit configured to charge the first charging circuit and the second charging circuit out-of-phase from each other in response to an on signal from a ripple based constant-on-time DC-DC converter, where the voltage of the first charging circuit and the voltage of the second charging circuit are provided at the ripple voltage output as the ripple voltage.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventor: Shufan Chan
  • Publication number: 20180115157
    Abstract: One example discloses a power management device, including: a first port configured to be coupled to a first power source; a second port configured to be coupled to a second power source; a switched capacitor converter; and an inductor coupled in parallel with a switch; wherein the switched capacitor converter is coupled between the first port and one end of the inductor coupled in parallel with the switch; and wherein another end of the inductor coupled in parallel with the switch, is coupled between the switched capacitor converter and the second port.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 26, 2018
    Inventors: Shufan Chan, Nicholas Seroff, Kisun Lee, Chae Kun Lee
  • Patent number: 9941792
    Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Patent number: 9866115
    Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 9, 2018
    Assignee: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Publication number: 20170288537
    Abstract: Embodiments of a circuit for use with a DC-DC converter are disclosed. In an embodiment, a circuit for controlling frequency variation for a ripple based, constant-on time DC-DC converter, is discloses. The circuit includes a set/reset (SR) latch, a comparator configured to set the SR latch, and an on-time and frequency variation controller configured to reset the SR latch. The on-time and frequency variation controller includes a feedback loop configured to increase the rate at which a ramp voltage increases to reduce the time it takes for the ramp voltage to exceed a threshold voltage. Embodiments of a method for controlling frequency variation for a ripple based, constant-on time DC-DC converter are also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Publication number: 20170288543
    Abstract: Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicant: NXP B.V.
    Inventors: Yue Jing, Ahmad Dashtestani, Shufan Chan
  • Patent number: 8212599
    Abstract: A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 3, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Ekram H. Bhuiyan, Shufan Chan
  • Publication number: 20110156760
    Abstract: A signal generating circuit and method are disclosed that do not require a phase-locked-loop and a low frequency temperature-stable oscillator. The method may include generating an oscillating output signal responsive to a feedback signal, where the feedback signal controls a frequency of the oscillating output signal, generating a current output signal having a magnitude corresponding to the frequency of the oscillating output signal, and then comparing the current output signal to a reference signal to generate the feedback signal. The signal generating circuit may include an oscillator circuit responsive to a feedback signal and a frequency-to-current conversion circuit configured to generate a frequency dependent current signal that is compared to a reference current to generate an output signal corresponding to the frequency of the oscillating output signal. A feedback conversion circuit compares the output signal with a reference signal to generate the feedback signal to the oscillator circuit.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Ekram H. Bhuiyan, Shufan Chan
  • Patent number: 7823116
    Abstract: In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip.
    Type: Grant
    Filed: June 2, 2007
    Date of Patent: October 26, 2010
    Assignee: SynCira Corporation
    Inventor: Shufan Chan
  • Publication number: 20090300570
    Abstract: In one embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip. In response to user preference directives, methods and apparatus are disclosed to perform re-synthesis of analog circuit layouts in another embodiment of the invention.
    Type: Application
    Filed: July 16, 2007
    Publication date: December 3, 2009
    Applicant: SYNCIRA CORPORATION
    Inventor: Shufan Chan
  • Publication number: 20080016476
    Abstract: In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip.
    Type: Application
    Filed: June 2, 2007
    Publication date: January 17, 2008
    Inventor: Shufan Chan
  • Publication number: 20080016483
    Abstract: In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipulating a hierarchical analog circuit layout including device placement and net routing in response to the circuit netlist, the hierarchical analog circuit layout including a plurality of levels of layout hierarchy; and passing layout information from one level of the layout hierarchy to an adjacent level of the layout hierarchy to synthesize the layout of the integrated circuit chip.
    Type: Application
    Filed: June 2, 2007
    Publication date: January 17, 2008
    Inventor: Shufan Chan
  • Patent number: 6198263
    Abstract: A dead time regulating apparatus is used in a switch mode power system. The apparatus, comprises a power MOSFET circuit with PMOS and NMOS devices. Driving means is connected for driving and for turning-on a delay in the MOSFETs. A time delay detecting means is connected for detecting dead time during MOSFET turn on and a pulse width comparing means is connected for receiving dead time signals and synchronous pulses for generating control signals. The control signals are directed to the driver means respectively for adjusting turn-on delays. The method of the invention provides precise dead time control in the MOSFET devices. The circuit drives the two MOSFET devices such that there is precise control of the dead time during on-off switching.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: March 6, 2001
    Assignee: Integrated Power Technologies, Inc.
    Inventor: Shufan Chan
  • Patent number: 5563501
    Abstract: An improved low voltage dropout regulation circuit is provided. The internal compensating capacitance coupled to the regulated output port is coupled to a virtual ground and the virtual ground is current buffered for coupling to the control electrode of the path element. For additional frequency compensation, particularly when the path element has a large capacitance, an additional internal compensating capacitance is coupled between the input of the dropout circuit and an output of a transconductance amplifier, which is responsive to the voltage at the regulated output port.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: October 8, 1996
    Assignee: Linfinity Microelectronics
    Inventor: Shufan Chan
  • Patent number: 5552697
    Abstract: An improved low voltage dropout regulation circuit is provided. The internal compensating capacitance coupled to the regulated output port is coupled to a virtual ground and the virtual ground is current buffered for coupling to the control electrode of the path element.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: September 3, 1996
    Assignee: Linfinity Microelectronics
    Inventor: Shufan Chan
  • Patent number: 5515006
    Abstract: An improved output stage for a CMOS circuit is disclosed. In particular, the circuit drives both output transistors of a push-pull output in class AB operation for efficient power usage with low noise and distortion with a minimal number of components.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: May 7, 1996
    Assignee: Linfinity Microelectronics, Inc.
    Inventor: Shufan Chan
  • Patent number: 5397945
    Abstract: A circuit for converting an input signal with an arbitrary duty cycle to an output signal with a 50 percent duty cycle. A bandpass filter removes unwanted DC and high frequency components from the input signal. A comparator compares the filtered signal to a reference voltage and provides very high gain amplification to produce an output signal having a 50 percent duty cycle. In one embodiment, two bandpass filters are used to condition the signal prior to providing it to the comparator. Each bandpass stage is comprised of a low pass filter followed by a high pass filter.
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: March 14, 1995
    Assignee: Samsung Semiconductor, Inc.
    Inventors: Daniel Shum, Shufan Chan
  • Patent number: 4888806
    Abstract: A computer speech system for digitally storing and reproducing representations of human speech. An analog waveform representative of a segment of speech is compressed for storage by storing companded differences between adjacent local maxima and minima of the waveform together with the lengths of time between the occurrences of the maxima and minima. The compressed speech is reproduced by looking up precomputed values in a lookup table according to the companded differences and times and furnishing the values from the lookup table to a digital-to-analog converter and thence to a conventional audio output device. The values are furnished to the converter by putting them on lower bits of the address bus and performing an operation at an address to which the converter responds.
    Type: Grant
    Filed: May 29, 1987
    Date of Patent: December 19, 1989
    Assignee: Animated Voice Corporation
    Inventors: Keith R. Jenkin, Shufan Chan