Patents by Inventor Shuichi Tanaka

Shuichi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8508042
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 13, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 8421248
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: April 16, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 8407406
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is disclosed.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shuichi Tanaka
  • Patent number: 8207056
    Abstract: A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: June 26, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 8183690
    Abstract: An electronic device including: a semiconductor chip on which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; a resin protrusion disposed on the semiconductor chip; an interconnect formed on the electrode and extending over the resin protrusion; a wiring board on which a wiring pattern is formed, the semiconductor chip being mounted on the wiring board so that part of the interconnect positioned over the resin protrusion faces and is electrically connected to the wiring pattern; and an adhesive that bonds the semiconductor chip and the wiring board. The resin protrusion is compressed in a direction in which the distance between the semiconductor chip and the wiring board decreases and is formed of a material having a negative coefficient of thermal expansion.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 22, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 8183693
    Abstract: A semiconductor device includes n1 first interconnects (n is an integer larger than one) respectively formed on first electrodes and extending over a first resin protrusion, and n2 second interconnects (n2<n1) respectively formed on second electrodes and extending over a second resin protrusion. The first and second resin protrusions are formed of an identical material, have an identical width, and extend longitudinally. The first interconnects extends to intersect a longitudinal axis of the first resin protrusion, and each of the first interconnects has a first width W1 on the first resin protrusion. The second interconnects extends to intersect a longitudinal axis of the second resin protrusion, and each of the second interconnects has a second width W2 (W1<W2) on the second resin protrusion. The relationship W1×n1=W2×n2 is satisfied.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: May 22, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito
  • Publication number: 20120104633
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi TANAKA
  • Patent number: 8142602
    Abstract: A method of forming a bonded structure comprises the steps of: mounting a semiconductor device having an electrode; a convexity protruding higher than the electrode and formed of a resin; and a conductive unit electrically coupled to the electrode and extending over the surface of the convexity, onto a specific substrate with an intermediary of a bonding material; and mounting the semiconductor device by hot pressing within a temperature range including the glass transition temperature of the resin.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: March 27, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Patent number: 8114788
    Abstract: A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: February 14, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi Tanaka, Nobuaki Hashimoto
  • Patent number: 8106509
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: January 31, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Shuichi Tanaka
  • Publication number: 20110161606
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is disclosed.
    Type: Application
    Filed: September 13, 2010
    Publication date: June 30, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shuichi TANAKA
  • Publication number: 20110136337
    Abstract: A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi TANAKA, Nobuaki HASHIMOTO
  • Publication number: 20110121451
    Abstract: An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.
    Type: Application
    Filed: January 27, 2011
    Publication date: May 26, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shuichi TANAKA
  • Patent number: 7936073
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 3, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Hideo Imai, Shuichi Tanaka
  • Patent number: 7910498
    Abstract: A method for manufacturing a semiconductor device, including: (a) forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; (b) fusing the resin layer without being cured and shrunk by a first energy supply processing; (c) forming a resin boss by curing and shrinking the resin layer after fusion by a second energy supply processing; and (d) forming an electrical conducting layer which is electrically connected to the electrode pad and passes through over the resin boss.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: March 22, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Yasuo Yamasaki, Shuichi Tanaka, Nobuaki Hashimoto
  • Patent number: 7888799
    Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: February 15, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Shuichi Tanaka, Haruki Ito, Yasuhito Aruga, Ryohei Tamura, Michiyoshi Takano
  • Publication number: 20110018110
    Abstract: A semiconductor device includes n1 first interconnects (n is an integer larger than one) respectively formed on first electrodes and extending over a first resin protrusion, and n2 second interconnects (n2<n1) respectively formed on second electrodes and extending over a second resin protrusion. The first and second resin protrusions are formed of an identical material, have an identical width, and extend longitudinally. The first interconnects extends to intersect a longitudinal axis of the first resin protrusion, and each of the first interconnects has a first width W1 on the first resin protrusion. The second interconnects extends to intersect a longitudinal axis of the second resin protrusion, and each of the second interconnects has a second width W2 (W1<W2) on the second resin protrusion. The relationship W1×n1=W2×n2 is satisfied.
    Type: Application
    Filed: October 4, 2010
    Publication date: January 27, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shuichi TANAKA, Haruki ITO
  • Publication number: 20110011630
    Abstract: A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.
    Type: Application
    Filed: September 27, 2010
    Publication date: January 20, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hideo IMAI, Shuichi TANAKA
  • Publication number: 20110008431
    Abstract: The present invention provides a tablet for treating postherpetic neuralgia and a method of treating postherpetic neuralgia with the use of the tablet. The therapeutic tablet for postherpetic neuralgia according to the present invention is characterized in comprising buprenorphine hydrochloride, having a double layer structure consisting of a quick-release layer and a sustained-release layer, wherein the tablet is adhesive to the oral mucosa.
    Type: Application
    Filed: March 14, 2008
    Publication date: January 13, 2011
    Applicants: TOYO BOSEKI KABUSHIKI KAISHA, FUSO PHARMACEUTICAL INDUSTRIES, LTD.
    Inventors: Takuji Fukuno, Hiroshi Tachimori, Fuminori Mukunoki, Tadayo Miyasaka, Hiromasa Araki, Shuichi Tanaka, Shingo Doi, Shoichi Kawazoe
  • Publication number: 20100313207
    Abstract: For a distributed application execution environment where the execution of a business process is accomplished by combining services in a manner that suits the business process to be executed, technologies have been developed to allocate hardware resources necessary to execute services that constitute a business process. With the conventional technologies, however, when using existing hardware resources is not enough to satisfy a requested execution quality of a service, the service is executed with a quality lower than the requested level. The present invention makes it possible to purvey IT resources flexibly in a distributed processing environment such that the requested level of business process execution quality is met. The present invention flexibly changes the configuration of IT resources that execute services constituting a business process, so that a requested quality of the business process is met.
    Type: Application
    Filed: March 15, 2010
    Publication date: December 9, 2010
    Inventors: Tadashi TANAKA, Yuichi Mori, Shuichi Tanaka, Yuki Kondo, Yusuke Jin, Keishi Oshima