Patents by Inventor Shuichiro Azuma

Shuichiro Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11461225
    Abstract: A storage device comprises a flash memory and processing circuitry. The processing circuitry is configured to divide a storage area into pages to manage the storage area, and deletes each of the blocks including a plurality of pages. The processing circuitry receives a write instruction including address information specifying a writing location of the data, and stores, with respect to a plurality of groups in which each group includes one or more blocks, a plurality of group identification information each identifying a group and information specifying blocks included in the group in association with each other. The processing circuitry performs a predetermined calculation to obtain group identification information, and identifies a group including a block including pages onto which data is to be written according to the write instruction. Finally, the processing circuitry writes the data onto the pages of the block included in the group identified.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 4, 2022
    Assignee: BUFFALO INC.
    Inventors: Kazuki Makuni, Shuichiro Azuma, Noriaki Sugahara, Yu Nakase
  • Publication number: 20210374051
    Abstract: A storage apparatus includes: a memory that stores data and main management information, the main management information identifying a physical address of the data; and processing circuitry configured to generate preliminary management information that includes information of the same content as the main management information, and select, as use management information, any one of the main management information and the preliminary management information upon start of the storage apparatus. Access to the data stored in the memory is performed using the selected use management information.
    Type: Application
    Filed: May 18, 2021
    Publication date: December 2, 2021
    Applicant: BUFFALO INC.
    Inventors: Kazuki MAKUNI, Shuichiro AZUMA
  • Publication number: 20200319999
    Abstract: A storage device comprises a flash memory and processing circuitry. The processing circuitry is configured to divide a storage area into pages to manage the storage area, and deletes each of the blocks including a plurality of pages. The processing circuitry receives a write instruction including address information specifying a writing location of the data, and stores, with respect to a plurality of groups in which each group includes one or more blocks, a plurality of group identification information each identifying a group and information specifying blocks included in the group in association with each other. The processing circuitry performs a predetermined calculation to obtain group identification information, and identifies a group including a block including pages onto which data is to be written according to the write instruction. Finally, the processing circuitry writes the data onto the pages of the block included in the group identified.
    Type: Application
    Filed: March 19, 2020
    Publication date: October 8, 2020
    Applicant: BUFFALO INC.
    Inventors: Kazuki MAKUNI, Shuichiro AZUMA, Noriaki SUGAHARA, Yu NAKASE
  • Patent number: 10657040
    Abstract: A storage device including a flash memory, and circuitry that manages a logical address and a physical address so as to be converted using a conversion table, writes a logical address and old and new information indicating a timing when the data is written, into the physical address together with the data, writes at least latest old and new information of the old and new information written in the block into a predetermined page of the block, and reestablishes the conversion table by arranging the logical address recorded in each page included in the block and the physical address corresponding to the logical address in association with each other, in chronological order of the latest old and new information read out from each block of the flash memory, at a predetermined reestablishment timing for performing reestablishment of the conversion table.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 19, 2020
    Assignee: BUFFALO INC.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yu Nakase
  • Patent number: 10528360
    Abstract: A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: January 7, 2020
    Assignee: BUFFALO INC.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Noriaki Sugahara, Yu Nakase
  • Patent number: 10403605
    Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 3, 2019
    Assignee: BUFFALO INC.
    Inventors: Yu Nakase, Takayuki Okinaga, Shuichiro Azuma, Kazuki Makuni, Takeshi Kotegawa, Noriaki Sugahara
  • Publication number: 20180357158
    Abstract: A storage device including a flash memory, and circuitry that manages a logical address and a physical address so as to be converted using a conversion table, writes a logical address and old and new information indicating a timing when the data is written, into the physical address together with the data, writes at least latest old and new information of the old and new information written in the block into a predetermined page of the block, and reestablishes the conversion table by arranging the logical address recorded in each page included in the block and the physical address corresponding to the logical address in association with each other, in chronological order of the latest old and new information read out from each block of the flash memory, at a predetermined reestablishment timing for performing reestablishment of the conversion table.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 13, 2018
    Applicant: BUFFALO INC.
    Inventors: Kazuki MAKUNI, Takayuki OKINAGA, Shuichiro AZUMA, Yu NAKASE
  • Publication number: 20180182737
    Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of electric wirings. The plurality of semiconductor chips are stacked in a first direction, each semiconductor chip of the plurality of semiconductor chips including a plurality of conductive pads that are aligned in an aligning direction, orthogonal to the first direction. The plurality of semiconductor chips are stacked such that each semiconductor chip is shifted from an adjacent semiconductor chip of the plurality of semiconductor chips by a first predetermined interval in the aligning direction and shifted from the adjacent semiconductor chip by a second predetermined interval in a second direction orthogonal to both the first direction and the aligning direction. The plurality of electric wirings electrically connect the plurality of conductive pads of every other semiconductor chip of the plurality of semiconductor chips, respectively.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Applicant: Buffalo Memory Co, Ltd.
    Inventors: YU NAKASE, Takayuki Okinaga, Shuichiro Azuma, Kazuki Makuni, Takeshi Kotegawa, Noriaki Sugahara
  • Publication number: 20180018182
    Abstract: A storage device includes a first memory which stores data including activation data necessary to activate a host device, a second memory, and a controller which performs writing and reading operation of data stored in the first memory based on a request from the host device; acquires address information including an address and data amount of data in the first memory, for which a read request is previously issued from the host device at activation of the host device; at activation of the storage device, reads data including at least the activation data from the first memory based on the address information and store the data in the second memory; and in response to a read request issued from the host device, transmits the data stored in the second memory to the host device.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 18, 2018
    Applicant: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki MAKUNI, Takayuki OKINAGA, Shuichiro AZUMA, Noriaki SUGAHARA, Yu NAKASE
  • Patent number: 9866219
    Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: January 9, 2018
    Assignees: MEISEI GAKUEN, BUFFALO MEMORY CO., LTD.
    Inventors: Kanji Otsuka, Yoichi Sato, Takayuki Okinaga, Shuichiro Azuma
  • Patent number: 9632714
    Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: April 25, 2017
    Assignee: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yosuke Takata, Noriaki Sugahara
  • Publication number: 20160211851
    Abstract: An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.
    Type: Application
    Filed: June 9, 2014
    Publication date: July 21, 2016
    Applicants: Meisei Gakuen, BUFFALO MEMORY CO., LTD.
    Inventors: Kanji OTSUKA, Yoichi SATO, Takayuki OKINAGA, Shuichiro AZUMA
  • Patent number: 9223695
    Abstract: An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: December 29, 2015
    Assignee: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yosuke Takata, Noriaki Sugahara
  • Patent number: 9189388
    Abstract: An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 17, 2015
    Assignee: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yosuke Takata, Noriaki Sugahara
  • Publication number: 20150242151
    Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 27, 2015
    Applicant: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki MAKUNI, Takayuki OKINAGA, Shuichiro AZUMA, Yosuke TAKATA, Noriaki SUGAHARA
  • Patent number: 9063845
    Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 23, 2015
    Assignee: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yosuke Takata, Noriaki Sugahara
  • Publication number: 20140068157
    Abstract: A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory.
    Type: Application
    Filed: August 9, 2013
    Publication date: March 6, 2014
    Applicant: BUFFALO MEMORY CO., LTD.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yosuke Takata, Noriaki Sugahara
  • Publication number: 20140006695
    Abstract: An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 2, 2014
    Inventors: Kazuki MAKUNI, Takayuki OKINAGA, Shuichiro AZUMA, Yosuke TAKATA, Noriaki SUGAHARA
  • Patent number: 8504762
    Abstract: A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 6, 2013
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Masahiro Matsumoto, Takayuki Okinaga, Shuichiro Azuma, Shigeru Takemura, Yasuyuki Koike, Kazuki Makuni
  • Patent number: 8291149
    Abstract: A storage device includes a drive selection section (1), a hard disk drive (HDD) (2), and a non-volatile memory drive (3). When an instruction such as a data I/O instruction is issued from a host such as a CPU (5) and an ATA controller (6) to the hard disk drive (HDD) (2), the drive selection section (1) receives the address value. If the address value is included in the address space predefined, the non-volatile memory drive (3) is made to execute the instruction. Otherwise, the hard disk drive (HDD) (2) is made to execute the instruction.
    Type: Grant
    Filed: July 5, 2004
    Date of Patent: October 16, 2012
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Shuichiro Azuma, Masahiro Matsumoto, Takayuki Okinaga, Shigeru Takemura, Yoshiyuki Kimata, Takayuki Kishimoto