Patents by Inventor Shuji Nishi

Shuji Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139682
    Abstract: A control device of a power supply system is configured to control inputting of electric power from a power system connected to a power distribution device to a plurality of strings connected to the power distribution device and outputting of electric power from the plurality of strings to the power system and to execute a process of stopping control for switching the at least one switching element between connection and disconnection on a string in which inputting of electric power and outputting of electric power are stopped out of the plurality of strings.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 5, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Juni Yasoshima, Junta Izumi, Kenji Kimura, Toshihiro Katsuda, Kohei Matsuura, Junichi Matsumoto, Shuji Tomura, Shigeaki Goto, Naoki Yanagizawa, Kyosuke Tanemura, Kazuo Ootsuka, Takayuki Ban, Hironobu Nishi
  • Patent number: 11101648
    Abstract: A power supply system includes a main line, a plurality of sweep modules, and a control unit. Each sweep module includes a battery module and a power circuit module. The power circuit module switches between connection and disconnection between the battery module and the main line. The control unit executes sweep control for sequentially switching the battery modules which are to be connected to the main line. The control unit maintains connection of a refreshing module which is to be subjected to refreshing charging/discharging to the main line while sweep control is being executed in a state in which the refreshing module is excluded in at least one of outputting of electric power to the outside and inputting of electric power from the outside.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 24, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Juni Yasoshima, Junta Izumi, Kenji Kimura, Toshihiro Katsuda, Kohei Matsuura, Junichi Matsumoto, Shuji Tomura, Shigeaki Goto, Naoki Yanagizawa, Kyosuke Tanemura, Kazuo Ootsuka, Takayuki Ban, Hironobu Nishi
  • Patent number: 11049469
    Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: June 29, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shige Furuta, Takahiro Yamaguchi, Hiroyuki Adachi, Shuji Nishi
  • Publication number: 20210181576
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, and a plurality of pixels. Each of the pixels has a reflection region for performing display in a reflective mode. The first substrate includes a pixel electrode provided in each of the pixels and a reflection layer positioned opposite to the liquid crystal layer with respect to the pixel electrode. The reflection layer has a first region positioned in each of the pixels and a second region positioned between any two pixels adjacent to each other. Voltages of an identical polarity are applied to the liquid crystal layer for any two pixels adjacent to each other in a row direction, for any two pixels adjacent to each other in a column direction, or for all the pixels.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 17, 2021
    Inventors: TAKAHIRO SASAKI, MING NI, TAKASHI SATOH, KEIICHI INA, SHUJI NISHI
  • Publication number: 20210150999
    Abstract: A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.
    Type: Application
    Filed: October 6, 2020
    Publication date: May 20, 2021
    Inventors: Yasushi SASAKI, Yuhichiroh MURAKAMI, Shige FURUTA, Takahiro YAMAGUCHI, Hiroyuki ADACHI, Shuji NISHI
  • Patent number: 11009756
    Abstract: A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 18, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Keiichi Ina, Shuji Nishi, Takashi Satoh
  • Publication number: 20210043152
    Abstract: A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 11, 2021
    Inventors: Takahiro YAMAGUCHI, Shuji NISHI, Shige FURUTA, Hiroyuki ADACHI, Nami NAGIRA
  • Publication number: 20200142269
    Abstract: A display device includes a reflective electrode, a driving circuit section, a wiring, and a wiring expansion section. The reflective electrode is divided into split electrodes arranged with spaces, which transmit light, respectively provided thereamong and reflects light. The driving circuit section drives the reflective electrode. The wiring is connected to at least the split electrodes and the driving circuit section and composed of a conductive material having a light transmission property. The wiring expansion section is formed to expand in the wiring to overlap the space.
    Type: Application
    Filed: October 25, 2019
    Publication date: May 7, 2020
    Inventors: KEIICHI INA, SHUJI NISHI, TAKASHI SATOH
  • Patent number: 9881688
    Abstract: A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 30, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi
  • Patent number: 9715940
    Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: July 25, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuhichiroh Murakami, Yasushi Sasaki, Shige Furuta, Shuji Nishi, Makoto Yokoyama
  • Patent number: 9632527
    Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: April 25, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi, Takahiro Yamaguchi, Makoto Yokoyama
  • Publication number: 20160027527
    Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Tr2 switches between whether or not to provide an output of an on-potential output unit 2 to a gate terminal of Tr1 in accordance with an output of a set control unit 3. The set control unit 3 controls a gate terminal of Tr2 into a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr1. The gate potential of Tr2 is raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr1, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.
    Type: Application
    Filed: February 17, 2014
    Publication date: January 28, 2016
    Inventors: Yuhichiroh MURAKAMI, Yasushi SASAKI, Shige FURUTA, Shuji NISHI, Makoto YOKOYAMA
  • Publication number: 20160018844
    Abstract: A shift register is configured by connecting unit circuits 1 in multiple stages. An output transistor Tr1 switches between whether or not to output a clock signal CKA in accordance with a gate potential. A drain terminal of an initialization transistor Tra is connected to a gate terminal of the Tr1, and a source terminal thereof is connected to an output terminal OUT or a clock terminal CKA. The source terminal of the Tra is connected to a node which has a low-level potential at the time of initialization and has a potential at the same level as the clock signal when the clock signal having a high-level potential is outputted. Thus, at the time of outputting the clock signal having the high-level potential, application of a high voltage between the source and the drain of the Tra is prevented, and degradation and breakdown of the initialization transistor are prevented.
    Type: Application
    Filed: February 17, 2014
    Publication date: January 21, 2016
    Inventors: Yasushi SASAKI, Yuhichiroh MURAKAMI, Shuji NISHI, Takahiro YAMAGUCHI, Makoto YOKOYAMA
  • Patent number: 9235092
    Abstract: In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 12, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takahiro Yamaguchi, Shige Furuta, Makoto Yokoyama, Shuji Nishi, Yohsuke Fujikawa
  • Publication number: 20150279480
    Abstract: Provided is a shift register with which an increase in power consumption can be inhibited, and with which malfunctions due to electric potential Modification Example between gate terminals of output transistors can be inhibited, while inhibiting an increase in circuit size. A bistable circuit of a shift register is provided with first to fourth transistors. In the third transistor, a gate terminal thereof is connected to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to a second input terminal, and a second conduction terminal thereof is connected to an output terminal. In the fourth transistor, a gate terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the gate terminal of the third transistor and the output terminal.
    Type: Application
    Filed: September 27, 2013
    Publication date: October 1, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuhichiroh Murakami, Yasushi Sasaki, Shuji Nishi
  • Publication number: 20150279481
    Abstract: A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal.
    Type: Application
    Filed: September 27, 2013
    Publication date: October 1, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasushi Sasaki, Yuhichiroh Murakami, Shuji Nishi
  • Publication number: 20150262703
    Abstract: Provided is a shift register capable of being driven using various clock signals, with low power consumption. A bistable circuit of a shift register is provided with first to third transistors, first to third input terminals, and an output terminal. In the first transistor, a gate terminal thereof and a first conduction terminal thereof are connected to the first input terminal. In the second transistor, a gate terminal thereof is connected to the third input terminal, and a first conduction terminal thereof is connected to the first input terminal. In the third transistor, a gate terminal thereof is connected respectively to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the output terminal.
    Type: Application
    Filed: September 27, 2013
    Publication date: September 17, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yuhichiroh Murakami, Yasushi Sasaki, Shuji Nishi
  • Publication number: 20150255171
    Abstract: An objective of the present invention is to provide a display device capable of suppressing consumption of the current flowing through gate clock signal bus lines by reducing the loads on the gate clock signal bus lines. In a shift register, which writes the voltages of a plurality of gate clock signals (CK1 to CK3) to gate bus lines (GL) via buffer circuits (BF), a plurality of gate clock signal bus lines (51a to 54a) are formed in an area between a display portion (600) and the buffer circuits (BF), independently of a clear signal bus line and other lines, so as to be adjacent to the buffer circuits (BF). This results in no area in which clear signal branch lines (61b) cross the gate clock signal bus lines (51a to 54a) and wiring lines in bistable circuits SR. Thus, it is possible to eliminate interlayer capacitance due to the crossings of the lines and fringe capacitance between the lines.
    Type: Application
    Filed: September 27, 2013
    Publication date: September 10, 2015
    Inventors: Shuji Nishi, Yuhichiroh Murakami, Yasushi Sasaki
  • Patent number: 9076400
    Abstract: A memory-type liquid crystal display device includes transistors (N1, N2), retention electrodes (MRY), refresh output control sections (RS1), and capacitors (Cb1). In a data retention period, an electric potential of each of the retention electrodes (MRY) is changed via a corresponding one of the capacitors (Cb1) by changing an electric potential level of a retention capacitor wire signal that is supplied to a corresponding CS line (CSL(i)). Each of the refresh output control sections (RS1) receives the electric potential thus changed of a corresponding one of the retention electrodes (MRY) via the input section and controls an electric potential of a corresponding pixel electrode (PIX) in accordance with the electric potential thus changed.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 7, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Eiji Matsuda, Yasushi Sasaki, Yuhichiroh Murakami, Seijirou Gyouten, Shuji Nishi, Makoto Yokoyama
  • Publication number: 20150022770
    Abstract: In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.
    Type: Application
    Filed: March 14, 2013
    Publication date: January 22, 2015
    Inventors: Takahiro Yamaguchi, Shige Furuta, Makoto Yokoyama, Shuji Nishi, Yohsuke Fujikawa