Abstract: A method of reducing electromagnetic interference in a semiconductor device includes: forming at least one functional circuit in a substrate of the semiconductor device; forming an integrated micro-shielding structure in the semiconductor device, the micro-shielding structure extending vertically through the substrate between a front surface and a back surface of the substrate and surrounding the functional circuit, the micro-shielding structure being configured to reduce radio frequency (RF) emissions in the semiconductor device and/or RF coupling between different functional parts of the functional circuit.

Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.

Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.

Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.

Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.

Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.

Abstract: An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.

Abstract: A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.

Abstract: An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of high output power, higher output impedance and lower matching loss. At the low voltage mode, it exhibits a reduced knee voltage so that some extra voltage and power can be gained although it is biased at lower voltage. The efficiency is therefore improved as well.

Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate.

Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.