Abstract: A memory device comprising memory cells associated with word lines for storing data. A timer is connected to determine the length of time during which a selected word line(s) is activated. The word line activation time length is shorter in a testing mode than in a using mode.

Abstract: A memory device comprising memory cells associated with word lines for storing data. A timer is connected to determine the length of time during which a selected word line(s) is activated. The word line activation time length is shorter in a testing mode than in a using mode.

Abstract: A memory device comprising memory cells associated with word lines for storing data. A timer is connected to determine the length of time during which a selected word line(s) is activated. The word line activation time length is shorter in a testing mode than in a using mode.

Abstract: A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Abstract: A static random access memory (SRAM) includes a pair of p-channel metal-oxide-semiconductor (PMOS) transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the PMOS transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d.c. current is suppressed and the voltage at the bit lines is prevented from being lowered. The variable resistor device can constitute a current mirror circuit along with a metal-insulator-semiconductor (MIS) transistor of the control circuit, so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances.

Abstract: A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.

Abstract: In a bit line driver for MOS memory units of a microcomputer, which is connected between a pair of complementary bit lines and provided with an equalizing MOS transistor, a pair of active-load MOS transistors and a pair of clamping MOS transistors are connected separately to the complementary bit lines, and further the area of the clamping MOS transistors is determined to be about three times greater than that of the active-load transistors. An increase in the area of the clamping MOS transistors serves to decrease the internal resistance thereof, so that the clamping operation can be improved. A decrease in area of the active-load MOS transistor serves to increase the internal resistance, so that the access time can be improved. In addition, the driver can operate stably in response to a low power clock pulse.