Patents by Inventor Shun-Miin (Sam) Wang

Shun-Miin (Sam) Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit
    Patent number: 7512851
    Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 31, 2009
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin (Sam) Wang, Ming-Tung Chang
  • Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
    Patent number: 7124342
    Abstract: A method for generating stimuli and test responses for testing faults in a scan-based integrated circuit in a selected scan-test mode or a selected self-test mode, the scan-based integrated circuit containing a plurality of scan chains, N clock domains, and C cross-clock domain blocks, each scan chain comprising multiple scan cells coupled in series, each clock domain having one capture clock, each cross-clock domain block comprising a combinational logic network.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: October 17, 2006
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Shun-Miin (Sam) Wang
  • Mask network design for scan-based integrated circuits
    Patent number: 7032148
    Abstract: A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The scan-based integrated circuit 207 contains a plurality of scan chains 221, a plurality of pattern generators 208, a plurality of pattern compactors 213, with each scan chain 221 comprising multiple scan cells 220, 222 coupled in series. The method and apparatus further includes an output-mask controller 211 and an output-mask network 212 embedded on the scan data input path of second selected scan cells 222, or a set/reset controller controlling selected set/reset inputs of second selected scan cells. A synthesis method is also proposed for synthesizing the output-mask controller 211 and the set/reset controller.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 18, 2006
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Shun-Miin (Sam) Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu