Patents by Inventor Shun Wu

Shun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8106721
    Abstract: A multilayer complementary-conducting-strip transmission line (CCS TL) structure is disclosed herein. The multilayer CCS TL structure includes a substrate, and n signal transmission lines being parallel and interlacing with n-1 mesh ground plane(s), therein a plurality of inter-media-dielectric (IMD) layers are correspondingly stacked with among the n signal transmission lines and the n-1 mesh ground plane(s) to form a stack structure on the substrate, therein n?2 and n is a natural number. Whereby, a multilayer CCS TL with independent of each layer and complete effect on signal shield is formed to provide more flexible for circuit design, reduce the circuit area and also diminish the transmission loss.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: January 31, 2012
    Assignees: National Taiwan University, CMSC, Inc.
    Inventors: Ching-Kuang Tzuang, Meng-Ju Chiang, Shian-Shun Wu
  • Patent number: 8106729
    Abstract: This invention discloses a complementary-conducting-strip transmission line (CCS TL) structure. The CCS TL structure includes a substrate, at least one first mesh ground plane, m second mesh ground planes having m first inter-media-dielectric (IMD) layers interlaced with and stacked among each other and the first mesh ground plane to form a stack structure on the substrate, a second IMD layer being on the stack structure, and a signal transmission line being on the second IMD layer. Wherein, each first IMD layer has a plurality of vias to correspondingly connect the first and the m second mesh ground planes, therein, m?2 and m is a natural number, and the m second mesh ground planes under the signal transmission line have at least one slit structure.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 31, 2012
    Assignees: National Taiwan University, CMSC, Inc.
    Inventors: Ching-Kuang Tzuang, Meng-Ju Chiang, Shian-Shun Wu
  • Patent number: 8101669
    Abstract: An exchange membrane containing modified maleimide oligomers comprising sulfonated poly(aryl ether ketone) (S-PAEK) and modified maleimide oligomers. The exchange membrane uses the modified maleimide oligomers having a hyper-branched architecture as matrix, and introduces them into S-PAEK to constitute semi-interpenetration network (semi-IPN), so as to intensify water holding capacity, chemical resistance, the electrochemical stability and thermal resistance of the ionic/proton exchange membrane. The exchange membrane can be used to fabricate the membrane electrode assemblies, fuel cells, and be applied them to the fields of seawater desalination, heavy water and sewage treatment, and biomass-energy resources.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 24, 2012
    Assignees: Industrial Technology Research Institute, National Central University
    Inventors: Jing-Pin Pan, Tsung-Hsiung Wang, Jung-Mu Hsu, Peter P. Chu, Chien-Shun Wu, Bo-Jun Liu
  • Patent number: 8085113
    Abstract: This invention discloses a complementary-conducting-strip coupled-line (CCS CL). The CCS CL includes a substrate, m layers of mesh ground planes interlacing with m?1 layer(s) of first inter-media-dielectric (IMD) to form a stack structure on the substrate, a second IMD layer being on the stack structure, and n metal lines being on the second IMD layer and being edge-coupled with each other. Wherein, the m?1 first IMD layer(s) has(have) a plurality of vias to connect matching mesh ground planes, therein, m?2 and m is a natural number, n?2 and n is a natural number.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: December 27, 2011
    Assignees: National Taiwan University, CMSC, Inc.
    Inventors: Ching-Kuang Tzuang, Meng-Ju Chiang, Shian-Shun Wu
  • Publication number: 20110298569
    Abstract: The invention discloses the variable attenuator with characteristics, comprising wide attenuation ranges; syntheses on group delays, and low variation of the group delay. The building blocks, which construct the variable attenuator, comprise internal matching networks, external matching networks, delay networks, protecting networks, biasing network, a power combining network, and variable impedance networks. The elements, which realize the internal matching networks, external matching networks, signal combining networks, comprise resistor, inductor, capacitor, and transmission lines. The elements, which realize the variable impedance networks, comprise n-channel field-effect transistor (FET), p-channel FET, n-type bipolar junction transistor (BJT), and p-type BJT. The elements of the variable attenuator can be either integrated on a semiconductor chip by using system-on-chip (SOC) technologies.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Inventors: Ching-Kuang Tzuang, Chao-Wei Wang, Shian-Shun Wu
  • Patent number: 8048810
    Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Wen Tsai, Jim Cy Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
  • Publication number: 20110250725
    Abstract: A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an electrically neutralized portion therein. Then, a hard mask layer with limited thickness is applied on the treated polysilicon gate electrode layer. A tilt angle ion implantation is thus performing on the substrate after patterning the hard mask layer and the treated polysilicon gate electrode to from a gate structure.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 13, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Matt YEH, Fan-Yi HSU, Shun Wu LIN, Hui OUYANG, Chi-Ming YANG
  • Publication number: 20110189847
    Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fang Wen Tsai, Jim C.Y. Huang, Shun Wu Lin, Li-Shiun Chen, Kuang-Yuan Hsu
  • Publication number: 20110143510
    Abstract: A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun Wu LIN, Peng-Soon Lim, Matt Yeh, Ouyang Hui
  • Publication number: 20110144974
    Abstract: A foreign language writing service method includes: recognizing, when a mixed text of foreign language portions and mother tongue portions is entered by a learner, the mother tongue portions from the mixed text; translating the mother tongue portions; combining a mother tongue translation result with the foreign language portions of the mixed text to generate a combined text; and providing the learner with the combined text of the mother tongue translation result and the foreign language portions of the mixed text.
    Type: Application
    Filed: June 29, 2010
    Publication date: June 16, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Ae SEO, Chang Hyun Kim, Seong Il Yang, Jinxia Huang, Sung Kwon Choi, Ki Young Lee, Yoon Hyung Roh, Oh Woog Kwon, Yun Jin, Ying Shun Wu, Eun Jin Park, Young Kil Kim, Sang Kyu Park
  • Publication number: 20110131032
    Abstract: A hybrid translation apparatus includes a source language input unit for generalizing an input source language sentence for each node; a statistics-based translation knowledge database(DB) for storing learning data generalized for each node to be acquired; a first translation result generating unit for transforming the source language sentence generalized for each node into a node expression using the statistics-based translation knowledge to generate a first translation result; and a second translation result generating unit for repeatedly performing the generation of a target word for each node on the first translation result using pattern-based knowledge to generate a second translation result as target words for the respective nodes.
    Type: Application
    Filed: January 4, 2010
    Publication date: June 2, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seong II Yang, Young Kil Kim, Chang Hyun Kim, Oh Woog Kwon, Yun Jin, Eun Jin Park, Young Ae Seo, Sung Kwon Choi, Jinxia Huang, Yoon Hyung Roh, Ying Shun Wu, Ki Young Lee, Sang Kyu Park
  • Publication number: 20110097867
    Abstract: A method of fabricating a semiconductor device is provided. In one embodiment, a gate structure is formed on a substrate, the gate structure having a gate dielectric layer and a first polysilicon layer formed above the gate dielectric layer. A passivation layer is formed above the first polysilicon layer. A second polysilicon layer is formed above the passivation layer. The second polysilicon layer and the passivation layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed.
    Type: Application
    Filed: June 21, 2010
    Publication date: April 28, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun Wu LIN, Matt YEH
  • Publication number: 20110074835
    Abstract: This invention provides a display module, an electronic device using the same, and a display method thereof. The display module used in the electronic device is used for displaying a status of an electronic element of the electronic device. The display module includes a light guiding unit, a plurality of light emitting units, and a control unit. The light guiding unit has a light incident surface and a light output surface. The light emitting units are disposed adjacent to the light incident surface. The control unit is coupled with the light emitting units and selectively uses one of a plurality of current combinations to control the light emitting units. Light emitted from the light emitting units enters into the light guiding unit from the light incident surface and passes through the light output surface to present a continuous display effect.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 31, 2011
    Inventors: Chun-Min He, Yu-Te Lin, Sin-Shun Wu
  • Patent number: 7915105
    Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 29, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Chung-Ming Wang, Chi-Chun Chen
  • Patent number: 7827675
    Abstract: A method of manufacturing an activated carbon fiber soft electric heating product for overcoming existing problems including uneven temperature rise and heat dissipation at surfaces of the product, unbendable feature, short life and poor safety. An activated carbon fiber cloth and a woven fiber cloth of the activated carbon fiber soft electric heating product are fixed by an epoxy resin layer, and a conducting copper net is disposed between the activated carbon fiber cloth and the epoxy resin layer and coupled to a power input wire. The manufacturing method includes the steps of: (1) spraying an epoxy resin on a surface of the woven fiber cloth, and bake-drying and hot pressing the woven fiber cloth; and (2) connecting the conducting copper net and the power input wire, laying the activated carbon fiber cloth, and performing a second-time hot pressing.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: November 9, 2010
    Inventors: Ching-Ling Pan, Yung-Shun Wu
  • Publication number: 20100240204
    Abstract: A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.
    Type: Application
    Filed: March 8, 2010
    Publication date: September 23, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Matt YEH, Shun Wu Lin, Hui Ouyang
  • Publication number: 20100170817
    Abstract: A sleeve seat, comprising a sleeve connector having a perforated hole and a penetrating piece having multiple penetrating poles and fixing poles; wherein the penetrating pole is used for penetrating into the perforated hole of the sleeve connector and fixed in the hole, and the fixing pole is used for engaging with the top of the sleeve connector. In the light of above, when the sleeve is sheathed onto the sleeve connectors of the main seat, the penetrating poles of the penetrating piece is able to pass through the sleeve and penetrate into the perforated hole to fix still, also the fixing pole is able to pass through the sleeve and engage with the top of the sleeve connector, so that the sleeve can be stably and tightly assembled to the main seat to prevent from the steal, meanwhile, the goals of the stability of assembly and the multiple purposes of use are achieved as well.
    Type: Application
    Filed: January 5, 2009
    Publication date: July 8, 2010
    Inventor: Lai-Shun WU
  • Publication number: 20100148885
    Abstract: This invention discloses a complementary-conducting-strip coupled-line (CCS CL). The CCS CL includes a substrate, m layers of mesh ground planes interlacing with m?1 layer(s) of first inter-media-dielectric (IMD) to form a stack structure on the substrate, a second IMD layer being on the stack structure, and n metal lines being on the second IMD layer and being edge-coupled with each other. Wherein, the m?1 first IMD layer(s) has(have) a plurality of vias to connect matching mesh ground planes, therein, m?2 and m is a nature number, n?2 and n is a nature number.
    Type: Application
    Filed: June 15, 2009
    Publication date: June 17, 2010
    Applicants: NATIONAL TAIWAN UNIVERSITY, CMSC, INC.
    Inventors: Ching-Kuang Tzuang, Meng-Ju Chiang, Shian-Shun Wu
  • Patent number: 7737854
    Abstract: A radio frequency identification tag is provided. The radio frequency identification tag includes a body and a cutting indication formed on the body. The body includes a substrate, an antenna disposed on the substrate and an integrated circuit disposed on the substrate and electrically connected to the antenna for performing a radio frequency communication. An extension of the cutting indication intersects with the antenna to separate the body into two parts after breaking.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: June 15, 2010
    Assignee: Yuen Foong Yu Paper Mfg. Co. Ltd.
    Inventors: Shun-Chi Chang, Min Shun Wu, Yung Sheng Kuo
  • Publication number: 20100141359
    Abstract: The present invention provides a complementary-conducting-strip (CCS) structure for miniaturizing microwave transmission line. The CCS structure comprises a substrate; a transmission part formed on the substrate, the transmission part consisted of M metal layers and at least one connecting arm extending from the metal layers to connect to an adjacent CCS structure, the M metal layers interlaminated M-1 dielectric layer(s) perforating a plurality of first metal vias to connect the M metal layers, wherein M?=2 and M is a nature number; and a frame part formed on the substrate, the frame part surrounding the transmission part and consisted of M-1 metal frame(s), the M-1 metal frame(s) interlaminated M-2 dielectric frame(s) perforating a plurality of second metal vias to connect the metal frames.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Inventors: Ching-Kuang Tzuang, Meng-Ju Chiang, Shian-Shun Wu