Patents by Inventor Shunichi Nakamura

Shunichi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210119008
    Abstract: A semiconductor device has: a semiconductor substrate; a drift layer of a first conductivity type; a well region of a second conductivity type; a high-concentration region of the second conductivity type, a source region of the first conductivity type; an insulating film provided on the drift layer; a first contact metal film in contact with the source region and the high-concentration region through a first opening provided in the insulating film; and a second contact metal film formed on a surface of the first contact metal film and contacting the high-concentration region through a second opening provided in the first contact metal film; a source electrode film formed on a surface of a contact metal layer including the first contact metal film and the second contact metal film. The first contact metal film includes titanium nitride, and the second contact metal film includes titanium.
    Type: Application
    Filed: April 11, 2018
    Publication date: April 22, 2021
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Teppei TAKAHASHI, Tetsuto INOUE, Akihiko SUGAI, Takashi MOCHIZUKI, Shunichi NAKAMURA
  • Publication number: 20210074827
    Abstract: A wide gap semiconductor device has: a drift layer 12 using a first conductivity type wide gap semiconductor material; a well region 20, being a second conductivity type and provided in the drift layer 12; a polysilicon layer 150 provided on the well region 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.
    Type: Application
    Filed: December 14, 2017
    Publication date: March 11, 2021
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi NAKAMURA
  • Publication number: 20200411680
    Abstract: A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.
    Type: Application
    Filed: March 29, 2018
    Publication date: December 31, 2020
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi NAKAMURA
  • Publication number: 20200357882
    Abstract: A semiconductor device includes: a drift layer of a first conductivity type which is made of silicon carbide; a junction region formed on one main surface of the drift layer; a junction termination extended region of the drift layer, the junction termination extended region being formed outside the junction region when the one main surface is viewed in plan view, and the junction termination extended region containing an impurity of a second conductivity type opposite to the first conductivity type; and a guard ring region of the drift layer, the guard ring region being formed at a position overlapping the junction termination extended region when the one main surface is viewed in plan view, and the guard ring region containing the impurity of the second conductivity type with a concentration that is higher than that of the junction termination extended region, wherein in the junction termination extended region, the concentration of the impurity of the second conductivity type in a depth direction from the o
    Type: Application
    Filed: February 13, 2018
    Publication date: November 12, 2020
    Inventors: Akihiko SHIBUKAWA, Yusuke MAEYAMA, Shunichi NAKAMURA
  • Publication number: 20200335618
    Abstract: A wide gap semiconductor device has: a drift layer 12 being a first conductivity type; a well region 20 being a second conductivity type and provided in the drift layer 12; a source region 31 provided in the well region 20; a gate insulating film 60 provided on the drift layer 12 and the well region 20; a field insulating film 62 provided between a gate insulating film 60 and the well region 20; a gate electrode 125 provided on the gate insulating film 60; and a gate pad 120 electrically connected to the gate electrode 125. The field insulating film 62 has a recessed part extending in a plane direction. The well region 20 has a well contact region 21 electrically connected to a source pad 110 provided in the recessed part.
    Type: Application
    Filed: November 13, 2017
    Publication date: October 22, 2020
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi NAKAMURA
  • Publication number: 20200279946
    Abstract: A wide gap semiconductor device has a drift layer 12 using wide gap semiconductor material being a first conductivity type; a plurality of well regions 20 being a second conductivity type and formed in the drift layer 12; a polysilicon layer 150 provided on the well regions 20 and on the drift layer 12 between the well regions 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.
    Type: Application
    Filed: November 13, 2017
    Publication date: September 3, 2020
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Shunichi NAKAMURA
  • Patent number: 10600869
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 24, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
  • Patent number: 10510841
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 17, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
  • Patent number: 10403497
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: September 3, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Fukuda, Yoshiyuki Watanabe, Shunichi Nakamura
  • Publication number: 20190252498
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
  • Publication number: 20180174835
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.
    Type: Application
    Filed: August 12, 2015
    Publication date: June 21, 2018
    Inventors: Yusuke FUKUDA, Yoshiyuki WATANABE, Shunichi NAKAMURA
  • Patent number: 9960228
    Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: May 1, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Shunichi Nakamura, Atsushi Ogasawara, Ryohei Osawa, Akihiko Shibukawa
  • Patent number: 9831316
    Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: November 28, 2017
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Publication number: 20170263697
    Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).
    Type: Application
    Filed: August 27, 2015
    Publication date: September 14, 2017
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Atsushi OGASAWARA, Ryohei OSAWA, Akihiko SHIBUKAWA
  • Publication number: 20170229541
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 10, 2017
    Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
  • Patent number: 9716168
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 25, 2017
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Patent number: 9640618
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 2, 2017
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Publication number: 20170040423
    Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.
    Type: Application
    Filed: July 10, 2015
    Publication date: February 9, 2017
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
  • Patent number: 9496366
    Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: November 15, 2016
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Maeyama, Yoshiyuki Watanabe, Shunichi Nakamura
  • Publication number: 20160293753
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.
    Type: Application
    Filed: September 24, 2014
    Publication date: October 6, 2016
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA