Patents by Inventor Shunichi Nakamura
Shunichi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10600869Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.Type: GrantFiled: September 18, 2015Date of Patent: March 24, 2020Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
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Patent number: 10510841Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.Type: GrantFiled: April 18, 2019Date of Patent: December 17, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
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Patent number: 10403497Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.Type: GrantFiled: August 12, 2015Date of Patent: September 3, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke Fukuda, Yoshiyuki Watanabe, Shunichi Nakamura
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Publication number: 20190252498Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.Type: ApplicationFiled: April 18, 2019Publication date: August 15, 2019Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
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Publication number: 20180174835Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.Type: ApplicationFiled: August 12, 2015Publication date: June 21, 2018Inventors: Yusuke FUKUDA, Yoshiyuki WATANABE, Shunichi NAKAMURA
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Patent number: 9960228Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).Type: GrantFiled: August 27, 2015Date of Patent: May 1, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke Maeyama, Shunichi Nakamura, Atsushi Ogasawara, Ryohei Osawa, Akihiko Shibukawa
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Patent number: 9831316Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.Type: GrantFiled: July 10, 2015Date of Patent: November 28, 2017Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
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Publication number: 20170263697Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).Type: ApplicationFiled: August 27, 2015Publication date: September 14, 2017Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Atsushi OGASAWARA, Ryohei OSAWA, Akihiko SHIBUKAWA
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Publication number: 20170229541Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.Type: ApplicationFiled: September 18, 2015Publication date: August 10, 2017Inventors: Shunichi NAKAMURA, Akihiko SUGAI, Tetsuto INOUE
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Patent number: 9716168Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.Type: GrantFiled: September 24, 2014Date of Patent: July 25, 2017Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
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Patent number: 9640618Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.Type: GrantFiled: September 24, 2014Date of Patent: May 2, 2017Assignee: Shindengen Electric Manufacturing Co., Ltd.Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
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Publication number: 20170040423Abstract: A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.Type: ApplicationFiled: July 10, 2015Publication date: February 9, 2017Applicant: Shindengen Electric Manufacturing Co., Ltd.Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
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Patent number: 9496366Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.Type: GrantFiled: October 8, 2013Date of Patent: November 15, 2016Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke Maeyama, Yoshiyuki Watanabe, Shunichi Nakamura
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Publication number: 20160293753Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.Type: ApplicationFiled: September 24, 2014Publication date: October 6, 2016Applicant: Shindengen Electric Manufacturing Co., Ltd.Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
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Publication number: 20160254356Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a greater depth than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds only a part of the gate trench 20 in the horizontal direction is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad 89 is disposed is a gate region.Type: ApplicationFiled: September 24, 2014Publication date: September 1, 2016Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Tetsuto INOUE, Akihiko SUGAI, Shunichi NAKAMURA
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Publication number: 20160056260Abstract: A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature of 1150° C. or above in a gas atmosphere including nitrogen and oxygen, and introducing highly-concentrated nitrogen to one surface of the SiC substrate while forming the thermal oxide film; forming a highly-concentrated n-type SiC layer on one surface of the SiC substrate such that the thermal oxide film is removed from one surface of the SiC substrate by etching and, thereafter, one surface of the SiC substrate is exposed to radicals so that Si—N bonded bodies and C—N bonded bodies on one surface of the SiC substrate are removed while leaving nitrogen introduced into a lattice of SiC out of highly-concentrated nitrogen introduced into one surface of the SiC substrate; and forming an ohmic electrode layer on one surface of the SiC substrate.Type: ApplicationFiled: October 8, 2013Publication date: February 25, 2016Inventors: Yusuke MAEYAMA, Yoshiyuki WATANABE, Shunichi NAKAMURA
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Patent number: 7273414Abstract: A loop track for racing objects is disposed at the center of a race game device, for example for a simulated horse race. A plurality of racing objects, such as race horses, run on the track. The X- and Y-directional positions of the race horses are detected by a separable position detecting means underlying the track. The separable position detecting means allows for easier maintenance, transport, assembly, and disassembly of the device. Information regarding the positions of the horses is displayed on a game screen. Players can write memos to themselves on individual game screens by pressing a trace over the game information on the game screen. A control unit provides game information corresponding to other races other than a current race, including future races, and players may select information corresponding to future races on the individual game screen.Type: GrantFiled: April 29, 2002Date of Patent: September 25, 2007Assignee: Sega Enterprises, Ltd.Inventors: Yuji Nagao, Takanori Akiyama, Naoki Kawajiri, Seiji Hayashi, Susumu Murata, Koji Yamaguchi, Yuji Ikeda, Mitsuru Todaiji, Yasuhiro Takagi, Shunichi Nakamura, Keiji Yano, Muneoki Kamata, Shingo Kataoka, Koji Osuka
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Publication number: 20020165017Abstract: A loop track 12 for race horses is disposed at the center of a horse race game device 10. Twelve race horses 14 run on the track 12. A gate 18 is disposed in a paddock 20 in the track 12. The gate 18 is advanced to a start point of the track 12 from the paddock 20. Twelve satellites 12 are disposed on three sides of the track 12. A large projector 24 for displaying images of developments, ect. of a race is disposed on one of the short sides of the track 12. Speakers 25 for live broadcasting, fanfares, BGM, etc. are disposed on both sides of the large projector. The horse race game device enables a larger number of running objects to be raced at once, whereby race developments are made more amusing.Type: ApplicationFiled: April 29, 2002Publication date: November 7, 2002Inventors: Yuji Nagao, Takanori Akiyama, Naoki Kawajiri, Seiji Hayashi, Susumu Murata, Koji Yamaguchi, Yuji Ikeda, Mitsuru Todaiji, Yasuhiro Takagi, Shunichi Nakamura, Keiji Yano, Muneoki Kamata, Shingo Kataoka, Koji Osuka
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Patent number: 6394898Abstract: A loop track for race horses is disposed at the center of a horse race game device. Twelve race horses run on the track. A gate is disposed in a paddock in the track. The gate is advanced to a start point of the track from the paddock. Twelve satellites are disposed on three sides of the track. A large projector for displaying images of developments, etc. of a race is disposed on one of the short sides of the track. Speakers for live broadcasting, fanfares, BGM, etc. are disposed on both sides of the large projector. The horse race game device enables a larger number of running objects to be raced at once, whereby race developments are made more amusing.Type: GrantFiled: July 29, 1998Date of Patent: May 28, 2002Assignee: Sega Enterprises Ltd.Inventors: Yuji Nagao, Takanori Akiyama, Naoki Kawajiri, Seiji Hayashi, Susumu Murata, Koji Yamaguchi, Yuji Ikeda, Mitsuru Todaiji, Yasuhiro Takagi, Shunichi Nakamura, Keiji Yano, Muneoki Kamata, Shingo Kataoka, Koji Osuka
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Patent number: 5976019Abstract: A traveling simulator capable of controlling in real time the movements of model traveling members, irrespective of a traveling speed of a carrier, is disclosed. The model traveling members, modeled after actual traveling objects, are placed moveably on a traveling plate, and the moveable carrier is disposed below the traveling plate. These model traveling members are tracted by the carrier via the attractive force between magnets provided on a lower surface of the traveling members and magnets provided on an upper surface of the carrier. The magnets on the side of the carrier and those, which are opposed to the magnets on the side of the model traveling members consist of magnets rotatable around vertical shafts. These magnets are provided on the sides of the model traveling members and carrier, two each respectively, so that each set of magnets are spaced from each other.Type: GrantFiled: September 25, 1997Date of Patent: November 2, 1999Assignee: Sega Enterprises, Ltd.Inventors: Yuji Ikeda, Susumu Murata, Shunichi Nakamura, Shinya Saito, Kaoru Igarashi