Patents by Inventor Shunqiang Gong
Shunqiang Gong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10553488Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: GrantFiled: September 21, 2017Date of Patent: February 4, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Patent number: 10439021Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. The substrate has first and second major surfaces. A capacitor is disposed in the substrate. The capacitor includes a first electrode, a second electrode and an insulator separating the first and second electrodes. The second electrode encloses the first electrode and the insulator.Type: GrantFiled: December 1, 2016Date of Patent: October 8, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan
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Patent number: 10128201Abstract: Devices and methods for forming a device are disclosed. At least one die is provided. A redistribution layer having a fan-out region extends concentrically outwards from an outer perimeter of the at least one die. A seal ring is disposed in the fan-out region of the redistribution layer.Type: GrantFiled: February 16, 2017Date of Patent: November 13, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Shan Gao
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Publication number: 20180233462Abstract: Devices and methods for forming a device are disclosed. At least one die is provided. A redistribution layer having a fan-out region extends concentrically outwards from an outer perimeter of the at least one die. A seal ring is disposed in the fan-out region of the redistribution layer.Type: ApplicationFiled: February 16, 2017Publication date: August 16, 2018Inventors: Shunqiang GONG, Juan Boon TAN, Shan GAO
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Publication number: 20180158897Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. The substrate has first and second major surfaces. A capacitor is disposed in the substrate. The capacitor includes a first electrode, a second electrode and an insulator separating the first and second electrodes. The second electrode encloses the first electrode and the insulator.Type: ApplicationFiled: December 1, 2016Publication date: June 7, 2018Inventors: Shunqiang GONG, Juan Boon TAN
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Publication number: 20180012800Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: ApplicationFiled: September 21, 2017Publication date: January 11, 2018Inventors: Shunqiang GONG, Juan Boon TAN, Shijie WANG, Mahesh BHATKAR, Daxiang WANG
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Patent number: 9806128Abstract: An interposer for an integrated circuit includes a first side and a second side. The interposer includes a substrate and a via disposed in the substrate. A first electrical contact is disposed on the first side. A second electrical contact is disposed on the second side and electrically connected to the via. The interposer also includes a multiple-time programmable (“MTP”) element electrically connected to the first electrical contact and/or the via.Type: GrantFiled: May 22, 2015Date of Patent: October 31, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Juan Boon Tan, Yi Jiang, Danny Shum, Shunqiang Gong
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Patent number: 9799571Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes producing an interposer with an insulation plate and a plurality of through vias passing through the insulation plate. The interposer has a prime area and an in prime area. A prime area test circuit is formed in the prime area, where the prime area test circuit includes a portion of the plurality of through vias that are electrically connected in series.Type: GrantFiled: July 15, 2015Date of Patent: October 24, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan
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Patent number: 9773702Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: GrantFiled: December 28, 2015Date of Patent: September 26, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Patent number: 9711662Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.Type: GrantFiled: April 21, 2016Date of Patent: July 18, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Benfu Lin, Juan Boon Tan, Ramakanth Alapati
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Patent number: 9698200Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.Type: GrantFiled: October 7, 2016Date of Patent: July 4, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Pinghui Li, Ming Zhu, Shunqiang Gong, Wanbing Yi, Darin Chan, Yiang Aun Nga
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Publication number: 20170104029Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Pinghui LI, Ming ZHU, Shunqiang GONG, Wanbing YI, Darin CHAN, Yiang Aun NGA
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Publication number: 20170054039Abstract: Device and a method of forming a device are disclosed. The method includes providing a substrate. The substrate includes a buried oxide (BOX) layer having an initial thickness TB1 sandwiched in between a top surface layer and a base substrate. The top surface layer is processed to form one or more photonic devices and first and second isolation regions. An interlevel dielectric (ILD) layer is formed on the substrate. Through dielectric via (TDV) contacts extending from a top surface of the dielectric ILD layer to within the BOX layer of the substrate are formed. Lower and upper interconnect levels are formed on the ILD layer. A carrier substrate is provided over a top surface of the upper interconnect levels. The base substrate and a portion of the BOX layer are removed to expose a bottom surface of the TDV contacts.Type: ApplicationFiled: August 20, 2015Publication date: February 23, 2017Inventors: Shunqiang GONG, Juan Boon TAN, Ramakanth ALAPATI
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Publication number: 20170018468Abstract: Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes producing an interposer with an insulation plate and a plurality of through vias passing through the insulation plate. The interposer has a prime area and an in prime area. A prime area test circuit is formed in the prime area, where the prime area test circuit includes a portion of the plurality of through vias that are electrically connected in series.Type: ApplicationFiled: July 15, 2015Publication date: January 19, 2017Inventors: Shunqiang Gong, Juan Boon Tan
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Publication number: 20160343773Abstract: An interposer for an integrated circuit includes a first side and a second side. The interposer includes a substrate and a via disposed in the substrate. A first electrical contact is disposed on the first side. A second electrical contact is disposed on the second side and electrically connected to the via. The interposer also includes a multiple-time programmable (“MTP”) element electrically connected to the first electrical contact and/or the via.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: Juan Boon Tan, Yi Jiang, Danny Shum, Shunqiang Gong
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Patent number: 9437550Abstract: Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer includes an upper and lower level. The upper level of the dielectric layer is patterned to form at least first and second trench openings and alignment mark openings. One of the first and second trench openings serve as a through via (TV) trench while another trench opening serves as an interconnect trench. A TV opening aligned to the TV trench is formed. The TV opening extends partially into the substrate. A conductive layer is formed over the substrate to fill the trenches and the openings.Type: GrantFiled: December 16, 2013Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shunqiang Gong, Juan Boon Tan, Wei Liu, Hai Cong
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Publication number: 20160190041Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.Type: ApplicationFiled: December 28, 2015Publication date: June 30, 2016Inventors: Shunqiang Gong, Juan Boon Tan, Shijie Wang, Mahesh Bhatkar, Daxiang Wang
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Patent number: 9362171Abstract: Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.Type: GrantFiled: December 26, 2013Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shunqiang Gong, Juan Boon Tan, Wei Liu
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Patent number: 9240374Abstract: Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M1 to MX metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level MX includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having MX. The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between MX and its adjacent underlying metal level MX-1.Type: GrantFiled: December 30, 2013Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Wei Shao, Wanbing Yi, Shunqiang Gong, Chao Zhu, Juan Boon Tan
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Patent number: 9111941Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.Type: GrantFiled: May 30, 2013Date of Patent: August 18, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shunqiang Gong, Juan Boon Tan, Lei Wang, Wei Liu, Wanbing Yi, Jens Oswald