Patents by Inventor Shunsuke Doi

Shunsuke Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10052741
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a polishing table configured to hold a polishing pad for polishing a substrate, and to rotate the polishing pad. The apparatus further includes a dressing module configured to hold a dresser for dressing the polishing pad, and to dress a surface of the polishing pad by sweeping the polishing pad with the dresser while rotating the dresser. The apparatus further includes a controller configured to control a number of revolutions of the polishing table based on a position of the dresser to the polishing table, while the polishing pad is dressed.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Watanabe, Shunsuke Doi
  • Publication number: 20170259399
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a polishing table configured to hold a polishing pad for polishing a substrate, and to rotate the polishing pad. The apparatus further includes a dressing module configured to hold a dresser for dressing the polishing pad, and to dress a surface of the polishing pad by sweeping the polishing pad with the dresser while rotating the dresser. The apparatus further includes a controller configured to control a number of revolutions of the polishing table based on a position of the dresser to the polishing table, while the polishing pad is dressed.
    Type: Application
    Filed: August 2, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi WATANABE, Shunsuke DOI
  • Publication number: 20160056060
    Abstract: A cleaning member configured to clean a semiconductor substrate by relatively sliding over a surface of the semiconductor substrate is disclosed. The cleaning member includes a holding portion; and a brush portion supported by the holding portion and including an ion exchange resin.
    Type: Application
    Filed: February 19, 2015
    Publication date: February 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shunsuke DOI
  • Publication number: 20150273654
    Abstract: A polish pad for use in a chemical mechanical polishing including a polish layer having a polish surface configured to be capable of contacting a polish object, the polish layer including a coolant.
    Type: Application
    Filed: July 31, 2014
    Publication date: October 1, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shunsuke DOI
  • Patent number: 8084364
    Abstract: A method of fabricating a semiconductor device, includes forming an amorphous silicon film above a semiconductor substrate, partially removing the amorphous silicon film and partially removing the semiconductor substrate, thereby forming an element isolation trench in a surface of the semiconductor substrate, forming an insulating film above the amorphous silicon film so that the element isolation trench is filled with the insulating film, polishing the insulating film by a chemical-mechanical polishing method with the amorphous silicon film serving as a stopper, thereby planarizing an upper surface of the insulating film, and thermally-treating the amorphous silicon film, thereby converting the amorphous silicon film to a polysilicon film after polishing the insulating film.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Doi, Atsushi Shigeta
  • Publication number: 20110204433
    Abstract: A nonvolatile semiconductor storage device is disclosed. The nonvolatile semiconductor storage device includes a semiconductor substrate including a surface layer; an element isolation insulating film isolating the surface layer of the semiconductor device into a plurality of active regions; a first gate insulating film formed above the active regions; a charge storing layer formed above the first gate insulating film and including a silicon layer containing an upper layer selectively doped with carbon; a second gate insulating film formed above the charge storing layer; and a control gate electrode formed above the second gate insulating film.
    Type: Application
    Filed: November 30, 2010
    Publication date: August 25, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya FUJITA, Masayuki TANAKA, Shunsuke DOI
  • Patent number: 7829406
    Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes forming an insulating film above a semiconductor substrate having a recess and stopper film formed above the semiconductor substrate excluding the recess, thereby filling the recess with the insulating film, performing a first polishing by polishing the insulating film by means of a chemical mechanical polishing method using a first polishing liquid containing cerium oxide and first anionic surfactant, thereby obtaining a flattened surface, and performing a second polishing by polishing the flattened insulating film using a second polishing liquid containing cerium oxide and a second anionic surfactant having a smaller molecular weight than that of the first anionic surfactant under a polishing condition which differs from that of the first polishing, thereby exposing the stopper film.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Doi, Yukiteru Matsui
  • Publication number: 20100015777
    Abstract: A method of fabricating a semiconductor device, includes forming an amorphous silicon film above a semiconductor substrate, partially removing each of the amorphous silicon film and the semiconductor substrate, thereby forming an element isolation trench in a surface of the semiconductor substrate, forming an insulating film above the amorphous silicon film so that the element isolation trench is filled with the insulating film, polishing the insulating film by a chemical-mechanical polishing method with the amorphous silicon film serving as a stopper, thereby planarizing an upper surface of the insulating film, and thermally-treating the amorphous silicon film, thereby converting to a polysilicon film after polishing the insulating film.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 21, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shunsuke DOI, Atsushi Shigeta
  • Publication number: 20090075487
    Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes forming an insulating film above a semiconductor substrate having a recess and stopper film formed above the semiconductor substrate excluding the recess, thereby filling the recess with the insulating film, performing a first polishing by polishing the insulating film by means of a chemical mechanical polishing method using a first polishing liquid containing cerium oxide and first anionic surfactant, thereby obtaining a flattened surface, and performing a second polishing by polishing the flattened insulating film using a second polishing liquid containing cerium oxide and a second anionic surfactant having a smaller molecular weight than that of the first anionic surfactant under a polishing condition which differs from that of the first polishing, thereby exposing the stopper film.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 19, 2009
    Inventors: Shunsuke Doi, Yukiteru Matsui
  • Publication number: 20090068840
    Abstract: A polishing liquid is provided, which includes abrasive grains and a surfactant. The abrasive grains contain a first colloidal silica having an average primary particle diameter of 45-80 nm and a second colloidal silica having an average primary particle diameter of 10-25 nm. The weight w1 of the first colloidal silica and the weight w2 of the second colloidal silica satisfy the relationship represented by the following expression 1. 0.63?w1/(w1+w2)?0.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 12, 2009
    Inventors: Gaku MINAMIHABA, Shunsuke Doi, Nobuyuki Kurashima, Yoshikuni Tateyama, Hiroyuki Yano
  • Publication number: 20080020683
    Abstract: A polishing method includes polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part, and after polishing, separating the target object from the polishing pad at a position in contact with the cutout part.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 24, 2008
    Inventors: Shunsuke Doi, Hiroyuki Yano