Abstract: A sound reproducing method used in sound reproducing apparatus that includes the steps outlined below is provided. A sound signal is generated with a 3D sound generating process according to listener data and sound data. Pre-recorded sound data is retrieved to further generate a target distance function corresponding to the sound distance. A fixed head-related transfer function corresponding to a fixed distance is retrieved. A target head-related transfer function corresponding to the sound distance is generated by adapting the target distance function to the fixed head-related transfer function. The sound signal is reproduced by multiplying the sound signal by the target head-related transfer function.

Abstract: A sound reproducing method used in sound reproducing apparatus that includes the steps outlined below is provided. A sound signal is generated with a 3D sound generating process according to listener data and sound data. Pre-recorded sound data is retrieved to further generate a target distance function corresponding to the sound distance. A fixed head-related transfer function corresponding to a fixed distance is retrieved. A target head-related transfer function corresponding to the sound distance is generated by adapting the target distance function to the fixed head-related transfer function. The sound signal is reproduced by multiplying the sound signal by the target head-related transfer function.

Abstract: An integrated circuit (IC) device includes an IC and an electrostatic discharge (ESD) protection device. The IC has a substrate, a core and a power mesh. The power mesh has a power electrode, a grounding electrode and a seal ring. The core is formed inside the grounding electrode. The power electrode is formed between the seal ring and the grounding electrode. The ESD protection device has multiple switch triggering units, multiple switching units and multiple discharging units formed on the substrate and electrically connected between the power electrode and the grounding electrode. The switching units turn on corresponding discharging units upon detecting occurrence of ESD to guide static electricity on the power electrode to the grounding electrode, thereby preventing the core from being damaged by static electricity.

Abstract: An integrated circuit (IC) device includes an IC and an electrostatic discharge (ESD) protection device. The IC has a substrate, a core and a power mesh. The power mesh has a power electrode, a grounding electrode and a seal ring. The core is formed inside the grounding electrode. The power electrode is formed between the seal ring and the grounding electrode. The ESD protection device has multiple switch triggering units, multiple switching units and multiple discharging units formed on the substrate and electrically connected between the power electrode and the grounding electrode. The switching units turn on corresponding discharging units upon detecting occurrence of ESD to guide static electricity on the power electrode to the grounding electrode, thereby preventing the core from being damaged by static electricity.

Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.

Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.

Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.

Abstract: A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus.