Abstract: Provided is a semiconductor device including a semiconductor chip which has a main surface, a high potential region which is formed in a surface layer portion of the main surface, a low potential region which is formed in the surface layer portion of the main surface at an interval from the high potential region, a first conductive type drift region which is formed in a region between the high potential region and the low potential region in the surface layer portion of the main surface, and a first conductive type resurf region which is formed partially in a surface layer portion of the drift region such as to expose a part of a region which serves as a current path in the drift region from the main surface and which has an impurity concentration higher than that of the drift region.

Abstract: A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

Abstract: A semiconductor device including a semiconductor layer, a drain region formed at a surface region of the semiconductor layer, and a source/gate region including a source region and a gate region, which are alternatively arranged so as to be electrically connected to each other. The device further includes a resistive field plate that is disposed on the semiconductor layer between the drain region and the source/gate region and spirally wound in a top view. The field plate including an innermost peripheral portion electrically connected to the drain region and an outermost peripheral portion electrically connected to ground. An outermost peripheral ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the source/gate region. Additionally, a second ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the outermost ground conductor film.

Abstract: A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

Abstract: A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

Abstract: A semiconductor device including a semiconductor layer, a drain region formed at a surface region of the semiconductor layer, and a source/gate region including a source region and a gate region, which are alternatively arranged so as to be electrically connected to each other. The device further includes a resistive field plate that is disposed on the semiconductor layer between the drain region and the source/gate region and spirally wound in a top view. The field plate including an innermost peripheral portion electrically connected to the drain region and an outermost peripheral portion electrically connected to ground. An outermost peripheral ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the source/gate region. Additionally, a second ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the outermost ground conductor film.

Abstract: A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential.