Abstract: Structures employing siloxane epoxy polymers as diffusion barriers adjacent conductive metal layers are disclosed. The siloxane epoxy polymers exhibit excellent adhesion to conductive metals, such as copper, and provide an increase in the electromigration lifetime of metal lines. In addition, the siloxane epoxy polymers have dielectric constants less then 3, and thus, provide improved performance over conventional diffusion barriers.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: Semiconductor devices employing siloxane epoxy polymers as low-? dielectric films are disclosed. The devices include a semiconductor substrate, one or more metal layers or structures and one or more dielectric films, wherein at least one dielectric film in the devices is a siloxane epoxy polymer. Use of siloxane epoxy polymers is advantageous, in part, because the polymers adhere well to metals and have dielectric constants as low as 1.8. Thus, the disclosed semiconductor devices offer much better performance than devices fabricated using conventional dielectric materials. Furthermore, the siloxane epoxy polymer dielectrics are fully curable at low temperatures, exhibit low leakage currents, and remain stable at temperatures greater than 400° C.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: A method for preventing migration of metal ions into a dielectric layer comprising low-&kgr; siloxane polymer includes treating at least one surface of the dielectric layer with a plasma selected from nitrogen, nitrogen oxides, noble gases and mixtures thereof, and forming on the treated surface a barrier layer. The barrier layer prevents migration of metal ions into the dielectric layer.

Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

Abstract: The present invention provides a diffusion barrier in an integrated circuit. The diffusion barrier comprises a self-assembled monolayer. The diffusion barrier is preferably less than 5 nm thick; more preferably it is less than 2 nm thick. The self-assembled monolayer typically contains an aromatic group at its terminus.

Abstract: The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.

Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

Abstract: A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.

Abstract: A system for performing chemical mechanical planarization for a semiconductor wafer includes a chemical mechanical polishing system including a chemical mechanical polishing slurry. The system also includes a device for measuring the electrochemical potential of the slurry during processing which is electrically connected to the slurry, and a device for detecting the end point of the process, based upon the electrochemical potential of the slurry, which is responsive to the electrochemical potential measuring device. Accurate in situ control of a chemical mechanical polishing process is thereby provided.

Abstract: It has been found that stress in X-ray transparent films used to form masks for X-ray lithography also cause distortions of the film and of the high-resolution X-ray-absorptive pattern formed thereon. A method is disclosed which anneals boron nitride films for use in X-ray masks in such a way as to control stress.

Abstract: Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum. Reliable low-resistance contacts to VLSI devices are thereby provided in a cost-effective fabrication sequence.Other metallization systems, comprising a silicide and a diffusion barrier to aluminum formed in a single processing step, are also described.

Abstract: In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2).

Abstract: Silicon-rich silicides of titanium and tantalum have been found to be suitable for use as the gate metal in semiconductor integrated circuits replacing polysilicon altogether. Such silicon-rich silicides, formed by sintering a cosputtered alloy with silicon to metal ratio of three as in deposited film, are stable even on gate oxide. The use of these compounds leads to stable, low resistivity gates and eliminates the need for the high resistivity polysilicon gate.

Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.

Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.