Patents by Inventor Shye-Lin Wu

Shye-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7491633
    Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: February 17, 2009
    Assignees: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 7368371
    Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n? silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 6, 2008
    Assignee: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Publication number: 20070290234
    Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventor: Shye-Lin Wu
  • Publication number: 20070293001
    Abstract: A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n? silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventor: Shye-Lin Wu
  • Publication number: 20070293028
    Abstract: A method of forming a power Schottky rectifier device is disclosed. The Schottky rectifier device including LOCOS structure and two p doped layers formed thereunder to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination field oxide region formed into the n? drift layer and each spaced from each other by the mesas. A stack of metal layers formed of Ti/Ni/Ag are formed atop the front surface. A RTP (rapid thermal process) is then followed to form a Schottky barrier diode. Alternatively, the stack metal layers are formed of Ti/TiN/Al. Yet, the Al is formed after RTP. Subsequently, the top metal layer is patterned to form an anode electrode.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 20, 2007
    Inventor: Shye-Lin Wu
  • Patent number: 7187046
    Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: March 6, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Cheng Wu, Shye-Lin Wu
  • Patent number: 7078780
    Abstract: A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: July 18, 2006
    Assignees: Chip Integration Tech., Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 7064408
    Abstract: A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: June 20, 2006
    Assignees: Chip Integration Tech Co., Ltd.
    Inventor: Shye-Lin Wu
  • Patent number: 6998694
    Abstract: A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: February 14, 2006
    Assignees: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Publication number: 20050230744
    Abstract: A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 20, 2005
    Inventor: Shye-Lin Wu
  • Patent number: 6936905
    Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n? drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n? drift layer; a pair of field oxide regions and termination region formed into the n? drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: August 30, 2005
    Assignees: Chip Integration Tech Co., Ltd.
    Inventor: Shye-Lin Wu
  • Publication number: 20050127464
    Abstract: A power Schottky rectifier device having pluralities of trenches are disclosed. The Schottky barrier rectifier device includes field oxide region having p-doped region formed thereunder to avoid premature of breakdown voltage and having a plurality of trenches formed in between field oxide regions to increase the anode area thereto increase forward current capacity or to shrinkage the planar area for driving the same current capacity. Furthermore, the trenches have rounded corners to alleviate current leakage and LOCOS region in the active region to relief stress during the bonding process. The processes for power Schottky barrier rectifier device including termination region formation need only three masks and thus can gain the benefits of cost down.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 16, 2005
    Inventor: Shye-Lin Wu
  • Publication number: 20050029614
    Abstract: A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode.
    Type: Application
    Filed: August 5, 2003
    Publication date: February 10, 2005
    Inventor: Shye-Lin Wu
  • Patent number: 6825073
    Abstract: A Schottky diode structure and a method of making the same are disclosed. The method comprises following steps: firstly, a semiconductor substrate having a first conductive layer and an epi-layer doped with the same type impurities is provided. Then a first oxide layer is form on the epi layer. A patterning step to pattern first oxide layer and recess the epi layer (optional) is then followed to define guard rings. After stripping the photoresist pattern, a polycrystalline silicon layer formation is then followed. A boron and/or BF2+ ion implant is then performed. Subsequently, a high temperature drive in process and oxidation process to oxidize the polycrystalline silicon layer and drive ions is then carried out. A second mask and etch steps are then performed to open the active regions. A metallization process is then done. A third mask and etch steps are then implemented to define anode. Finally, a backside metal layer is then formed and serves as a cathode.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: November 30, 2004
    Assignee: Chip Integration Tech Co., Ltd.
    Inventor: Shye-Lin Wu
  • Publication number: 20040211974
    Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p-type doping regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown voltage. The Schottky rectifier device comprises: an n− drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n-drift layer; a pair of field oxide regions and termination region formed into the n− drift layer and each spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Applicant: Chip Integration Tech. Co., Ltd.
    Inventor: Shye-Lin Wu
  • Publication number: 20040195628
    Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 7, 2004
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chung-Cheng Wu, Shye-Lin Wu
  • Patent number: 6770516
    Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: August 3, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung Cheng Wu, Shye-Lin Wu
  • Publication number: 20040048424
    Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape.
    Type: Application
    Filed: September 5, 2002
    Publication date: March 11, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung Cheng Wu, Shye-Lin Wu
  • Patent number: 6649308
    Abstract: The ultra-short channel transistor in a semiconductor substrate includes a gate structure that is formed on the substrate. Side-wall spacers are formed on the side walls of the gate structure as an impurities-diffusive source. Source and drain regions are formed in the substrate. A metal silicide contact is formed on the top surface of the gate structure, and on the surface of the source and drain regions. Extended source and drain regions are formed beneath the side-wall spacers and connect next to the source and drain regions.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: November 18, 2003
    Assignee: Texas Instruments-Acer Incorporated
    Inventor: Shye-Lin Wu
  • Patent number: 6569729
    Abstract: A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: May 27, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung-Cheng Wu, Shye-Lin Wu